2017-08-09 10:43:01 +02:00
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#include <gbm.h>
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2018-02-12 21:29:23 +01:00
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#include <stdlib.h>
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#include <wlr/util/log.h>
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2017-08-09 10:43:01 +02:00
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#include <xf86drm.h>
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#include <xf86drmMode.h>
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2017-09-30 08:03:34 +02:00
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#include "backend/drm/drm.h"
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2017-09-30 08:11:41 +02:00
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#include "backend/drm/iface.h"
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2017-09-30 08:03:34 +02:00
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#include "backend/drm/util.h"
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2017-08-09 10:43:01 +02:00
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struct atomic {
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drmModeAtomicReq *req;
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bool failed;
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};
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2020-05-09 18:46:17 +02:00
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static void atomic_begin(struct atomic *atom) {
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memset(atom, 0, sizeof(*atom));
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2017-08-09 10:43:01 +02:00
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2020-05-09 18:46:17 +02:00
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atom->req = drmModeAtomicAlloc();
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if (!atom->req) {
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wlr_log_errno(WLR_ERROR, "Allocation failed");
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atom->failed = true;
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return;
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2017-08-09 10:43:01 +02:00
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}
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}
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2020-05-09 18:46:17 +02:00
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static bool atomic_commit(struct atomic *atom,
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struct wlr_drm_connector *conn, uint32_t flags) {
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2020-12-09 14:31:06 +01:00
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struct wlr_drm_backend *drm = conn->backend;
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2017-08-09 10:43:01 +02:00
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if (atom->failed) {
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return false;
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}
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2020-05-09 18:46:17 +02:00
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int ret = drmModeAtomicCommit(drm->fd, atom->req, flags, drm);
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2021-04-06 15:44:32 +02:00
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if (ret != 0) {
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wlr_drm_conn_log_errno(conn,
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(flags & DRM_MODE_ATOMIC_TEST_ONLY) ? WLR_DEBUG : WLR_ERROR,
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"Atomic %s failed (%s)",
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2020-05-09 18:46:17 +02:00
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(flags & DRM_MODE_ATOMIC_TEST_ONLY) ? "test" : "commit",
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(flags & DRM_MODE_ATOMIC_ALLOW_MODESET) ? "modeset" : "pageflip");
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return false;
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2017-08-09 10:43:01 +02:00
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}
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2020-05-09 18:46:17 +02:00
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return true;
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}
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2017-08-09 10:43:01 +02:00
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2020-05-09 18:46:17 +02:00
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static void atomic_finish(struct atomic *atom) {
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drmModeAtomicFree(atom->req);
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2017-08-09 10:43:01 +02:00
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}
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2020-02-11 00:38:43 +01:00
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static void atomic_add(struct atomic *atom, uint32_t id, uint32_t prop, uint64_t val) {
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2017-08-09 10:43:01 +02:00
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if (!atom->failed && drmModeAtomicAddProperty(atom->req, id, prop, val) < 0) {
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2018-07-09 23:49:54 +02:00
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wlr_log_errno(WLR_ERROR, "Failed to add atomic DRM property");
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2017-08-09 10:43:01 +02:00
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atom->failed = true;
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}
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}
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2020-05-07 21:11:43 +02:00
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static bool create_mode_blob(struct wlr_drm_backend *drm,
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2021-04-06 17:14:17 +02:00
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struct wlr_drm_connector *conn, const struct wlr_output_state *state,
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uint32_t *blob_id) {
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if (!drm_connector_state_active(conn, state)) {
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2020-05-07 21:11:43 +02:00
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*blob_id = 0;
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return true;
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}
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2021-04-06 17:14:17 +02:00
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if (drmModeCreatePropertyBlob(drm->fd, &conn->crtc->pending.mode->drm_mode,
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2020-05-07 21:11:43 +02:00
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sizeof(drmModeModeInfo), blob_id)) {
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wlr_log_errno(WLR_ERROR, "Unable to create mode property blob");
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return false;
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}
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return true;
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}
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2020-05-07 17:50:40 +02:00
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static bool create_gamma_lut_blob(struct wlr_drm_backend *drm,
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2020-05-14 18:27:02 +02:00
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size_t size, const uint16_t *lut, uint32_t *blob_id) {
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if (size == 0) {
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2020-05-07 17:50:40 +02:00
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*blob_id = 0;
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return true;
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}
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struct drm_color_lut *gamma = malloc(size * sizeof(struct drm_color_lut));
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if (gamma == NULL) {
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wlr_log(WLR_ERROR, "Failed to allocate gamma table");
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return false;
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}
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2020-05-14 18:27:02 +02:00
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const uint16_t *r = lut;
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const uint16_t *g = lut + size;
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const uint16_t *b = lut + 2 * size;
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2020-05-07 17:50:40 +02:00
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for (size_t i = 0; i < size; i++) {
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gamma[i].red = r[i];
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gamma[i].green = g[i];
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gamma[i].blue = b[i];
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}
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if (drmModeCreatePropertyBlob(drm->fd, gamma,
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size * sizeof(struct drm_color_lut), blob_id) != 0) {
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2020-05-14 18:27:02 +02:00
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wlr_log_errno(WLR_ERROR, "Unable to create gamma LUT property blob");
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2020-05-07 17:50:40 +02:00
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free(gamma);
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return false;
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}
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free(gamma);
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return true;
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}
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2020-05-18 10:34:24 +02:00
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static void commit_blob(struct wlr_drm_backend *drm,
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uint32_t *current, uint32_t next) {
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if (*current == next) {
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return;
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}
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if (*current != 0) {
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drmModeDestroyPropertyBlob(drm->fd, *current);
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}
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*current = next;
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}
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static void rollback_blob(struct wlr_drm_backend *drm,
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uint32_t *current, uint32_t next) {
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if (*current == next) {
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return;
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}
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if (next != 0) {
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drmModeDestroyPropertyBlob(drm->fd, next);
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}
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}
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2020-02-12 09:25:40 +01:00
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static void plane_disable(struct atomic *atom, struct wlr_drm_plane *plane) {
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2017-08-09 10:43:01 +02:00
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uint32_t id = plane->id;
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const union wlr_drm_plane_props *props = &plane->props;
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2020-02-12 09:25:40 +01:00
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atomic_add(atom, id, props->fb_id, 0);
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atomic_add(atom, id, props->crtc_id, 0);
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}
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static void set_plane_props(struct atomic *atom, struct wlr_drm_backend *drm,
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struct wlr_drm_plane *plane, uint32_t crtc_id, int32_t x, int32_t y) {
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uint32_t id = plane->id;
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const union wlr_drm_plane_props *props = &plane->props;
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struct wlr_drm_fb *fb = plane_get_next_fb(plane);
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2020-12-22 17:07:29 +01:00
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if (fb == NULL) {
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2020-12-15 12:21:40 +01:00
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wlr_log(WLR_ERROR, "Failed to acquire FB");
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2020-02-12 09:25:40 +01:00
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goto error;
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}
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2017-08-09 10:43:01 +02:00
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2020-12-18 16:24:36 +01:00
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uint32_t width = gbm_bo_get_width(fb->bo);
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uint32_t height = gbm_bo_get_height(fb->bo);
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2017-08-09 10:43:01 +02:00
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// The src_* properties are in 16.16 fixed point
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atomic_add(atom, id, props->src_x, 0);
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atomic_add(atom, id, props->src_y, 0);
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2020-12-18 16:24:36 +01:00
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atomic_add(atom, id, props->src_w, (uint64_t)width << 16);
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atomic_add(atom, id, props->src_h, (uint64_t)height << 16);
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atomic_add(atom, id, props->crtc_w, width);
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atomic_add(atom, id, props->crtc_h, height);
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2020-12-15 12:21:40 +01:00
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atomic_add(atom, id, props->fb_id, fb->id);
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2017-08-09 10:43:01 +02:00
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atomic_add(atom, id, props->crtc_id, crtc_id);
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2020-02-12 09:25:40 +01:00
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atomic_add(atom, id, props->crtc_x, (uint64_t)x);
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atomic_add(atom, id, props->crtc_y, (uint64_t)y);
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return;
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error:
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2020-05-07 12:08:26 +02:00
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wlr_log(WLR_ERROR, "Failed to set plane %"PRIu32" properties", plane->id);
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2020-02-12 09:25:40 +01:00
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atom->failed = true;
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2017-08-09 10:43:01 +02:00
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}
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2020-05-07 19:20:56 +02:00
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static bool atomic_crtc_commit(struct wlr_drm_backend *drm,
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2021-04-06 16:32:01 +02:00
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struct wlr_drm_connector *conn, const struct wlr_output_state *state,
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uint32_t flags) {
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2020-05-14 18:27:02 +02:00
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struct wlr_output *output = &conn->output;
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2020-02-12 09:25:40 +01:00
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struct wlr_drm_crtc *crtc = conn->crtc;
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2021-04-06 17:06:37 +02:00
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bool modeset = drm_connector_state_is_modeset(state);
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2021-04-06 17:14:17 +02:00
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bool active = drm_connector_state_active(conn, state);
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2021-04-06 17:06:37 +02:00
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2020-05-18 10:34:24 +02:00
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uint32_t mode_id = crtc->mode_id;
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2021-04-06 17:06:37 +02:00
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if (modeset) {
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2021-04-06 17:14:17 +02:00
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if (!create_mode_blob(drm, conn, state, &mode_id)) {
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2017-08-09 10:43:01 +02:00
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return false;
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}
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}
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2020-05-18 10:34:24 +02:00
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uint32_t gamma_lut = crtc->gamma_lut;
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2021-04-06 16:32:01 +02:00
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if (state->committed & WLR_OUTPUT_STATE_GAMMA_LUT) {
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2020-05-14 18:27:02 +02:00
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// Fallback to legacy gamma interface when gamma properties are not
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// available (can happen on older Intel GPUs that support gamma but not
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// degamma).
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2020-05-07 17:50:40 +02:00
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if (crtc->props.gamma_lut == 0) {
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2020-05-14 18:27:02 +02:00
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if (!drm_legacy_crtc_set_gamma(drm, crtc,
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2021-04-06 16:32:01 +02:00
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state->gamma_lut_size,
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state->gamma_lut)) {
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2020-05-07 17:50:40 +02:00
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return false;
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}
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} else {
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2021-04-06 16:32:01 +02:00
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if (!create_gamma_lut_blob(drm, state->gamma_lut_size,
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state->gamma_lut, &gamma_lut)) {
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2020-05-07 17:50:40 +02:00
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return false;
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}
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}
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}
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2020-05-27 16:43:19 +02:00
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bool prev_vrr_enabled =
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output->adaptive_sync_status == WLR_OUTPUT_ADAPTIVE_SYNC_ENABLED;
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bool vrr_enabled = prev_vrr_enabled;
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2021-04-06 16:32:01 +02:00
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if ((state->committed & WLR_OUTPUT_STATE_ADAPTIVE_SYNC_ENABLED) &&
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2020-05-27 16:43:19 +02:00
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drm_connector_supports_vrr(conn)) {
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2021-04-06 16:32:01 +02:00
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vrr_enabled = state->adaptive_sync_enabled;
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2020-05-27 16:43:19 +02:00
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}
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2021-04-06 17:06:37 +02:00
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if (modeset) {
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2018-01-15 21:49:37 +01:00
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flags |= DRM_MODE_ATOMIC_ALLOW_MODESET;
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2021-04-06 15:42:14 +02:00
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} else if (!(flags & DRM_MODE_ATOMIC_TEST_ONLY)) {
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2018-01-15 21:49:37 +01:00
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flags |= DRM_MODE_ATOMIC_NONBLOCK;
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}
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2017-08-09 10:43:01 +02:00
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2018-01-15 21:49:37 +01:00
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struct atomic atom;
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2020-05-09 18:46:17 +02:00
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atomic_begin(&atom);
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2021-04-06 17:14:17 +02:00
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atomic_add(&atom, conn->id, conn->props.crtc_id, active ? crtc->id : 0);
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if (modeset && active && conn->props.link_status != 0) {
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2018-10-04 14:11:37 +02:00
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atomic_add(&atom, conn->id, conn->props.link_status,
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DRM_MODE_LINK_STATUS_GOOD);
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}
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2020-05-18 10:34:24 +02:00
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atomic_add(&atom, crtc->id, crtc->props.mode_id, mode_id);
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2021-04-06 17:14:17 +02:00
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atomic_add(&atom, crtc->id, crtc->props.active, active);
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if (active) {
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2020-05-14 17:26:30 +02:00
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if (crtc->props.gamma_lut != 0) {
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2020-05-18 10:34:24 +02:00
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atomic_add(&atom, crtc->id, crtc->props.gamma_lut, gamma_lut);
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2020-05-14 17:26:30 +02:00
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}
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2020-05-27 16:43:19 +02:00
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if (crtc->props.vrr_enabled != 0) {
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atomic_add(&atom, crtc->id, crtc->props.vrr_enabled, vrr_enabled);
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}
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2020-05-07 21:11:43 +02:00
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set_plane_props(&atom, drm, crtc->primary, crtc->id, 0, 0);
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if (crtc->cursor) {
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2020-05-27 18:16:03 +02:00
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if (drm_connector_is_cursor_visible(conn)) {
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2020-05-07 21:11:43 +02:00
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set_plane_props(&atom, drm, crtc->cursor, crtc->id,
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conn->cursor_x, conn->cursor_y);
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} else {
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plane_disable(&atom, crtc->cursor);
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}
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}
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} else {
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plane_disable(&atom, crtc->primary);
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if (crtc->cursor) {
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2020-02-12 09:25:40 +01:00
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plane_disable(&atom, crtc->cursor);
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}
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}
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2020-02-11 00:38:43 +01:00
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2020-05-09 18:46:17 +02:00
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bool ok = atomic_commit(&atom, conn, flags);
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atomic_finish(&atom);
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2020-05-18 10:34:24 +02:00
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if (ok && !(flags & DRM_MODE_ATOMIC_TEST_ONLY)) {
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commit_blob(drm, &crtc->mode_id, mode_id);
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commit_blob(drm, &crtc->gamma_lut, gamma_lut);
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2020-05-27 16:43:19 +02:00
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if (vrr_enabled != prev_vrr_enabled) {
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output->adaptive_sync_status = vrr_enabled ?
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WLR_OUTPUT_ADAPTIVE_SYNC_ENABLED :
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WLR_OUTPUT_ADAPTIVE_SYNC_DISABLED;
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2020-12-24 17:55:45 +01:00
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wlr_drm_conn_log(conn, WLR_DEBUG, "VRR %s",
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vrr_enabled ? "enabled" : "disabled");
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2020-05-27 16:43:19 +02:00
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}
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2020-05-18 10:34:24 +02:00
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} else {
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rollback_blob(drm, &crtc->mode_id, mode_id);
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rollback_blob(drm, &crtc->gamma_lut, gamma_lut);
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}
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2020-05-09 18:46:17 +02:00
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return ok;
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2017-08-09 10:43:01 +02:00
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}
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2017-10-02 10:44:33 +02:00
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const struct wlr_drm_interface atomic_iface = {
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2020-05-07 19:20:56 +02:00
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.crtc_commit = atomic_crtc_commit,
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2017-08-09 10:43:01 +02:00
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};
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