2019-06-21 08:06:21 +02:00
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#define _XOPEN_SOURCE 700
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2017-05-01 05:20:48 +02:00
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#include <assert.h>
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2019-01-29 12:04:12 +01:00
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#include <drm_fourcc.h>
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2017-05-01 05:20:48 +02:00
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#include <drm_mode.h>
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2018-02-12 21:29:23 +01:00
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#include <errno.h>
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2017-05-01 05:20:48 +02:00
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#include <gbm.h>
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2017-08-07 11:07:42 +02:00
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#include <GLES2/gl2.h>
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#include <GLES2/gl2ext.h>
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2018-02-12 21:29:23 +01:00
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#include <inttypes.h>
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2019-08-09 15:20:52 +02:00
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#include <stdint.h>
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2018-02-12 21:29:23 +01:00
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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2019-06-21 08:06:21 +02:00
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#include <strings.h>
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2018-02-12 21:29:23 +01:00
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#include <time.h>
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2019-07-27 10:53:54 +02:00
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#include <wayland-server-core.h>
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2018-02-06 22:45:37 +01:00
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#include <wayland-util.h>
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2017-06-05 01:30:37 +02:00
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#include <wlr/backend/interface.h>
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2017-06-21 16:27:45 +02:00
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#include <wlr/interfaces/wlr_output.h>
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2018-02-12 21:29:23 +01:00
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#include <wlr/render/gles2.h>
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2018-03-19 23:16:29 +01:00
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#include <wlr/render/wlr_renderer.h>
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2018-03-15 09:11:03 +01:00
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#include <wlr/types/wlr_matrix.h>
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2018-02-12 21:29:23 +01:00
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#include <wlr/util/log.h>
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#include <xf86drm.h>
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#include <xf86drmMode.h>
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2019-10-26 22:35:51 +02:00
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#include "backend/drm/cvt.h"
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2017-09-30 08:03:34 +02:00
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#include "backend/drm/drm.h"
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2017-09-30 08:11:41 +02:00
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#include "backend/drm/iface.h"
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2017-09-30 08:03:34 +02:00
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#include "backend/drm/util.h"
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2018-02-12 21:29:23 +01:00
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#include "util/signal.h"
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2017-05-01 05:20:48 +02:00
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2018-04-26 00:24:58 +02:00
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bool check_drm_features(struct wlr_drm_backend *drm) {
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2018-10-01 22:44:33 +02:00
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uint64_t cap;
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2018-08-05 08:25:25 +02:00
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if (drm->parent) {
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if (drmGetCap(drm->fd, DRM_CAP_PRIME, &cap) ||
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!(cap & DRM_PRIME_CAP_IMPORT)) {
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wlr_log(WLR_ERROR,
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"PRIME import not supported on secondary GPU");
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return false;
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}
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if (drmGetCap(drm->parent->fd, DRM_CAP_PRIME, &cap) ||
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!(cap & DRM_PRIME_CAP_EXPORT)) {
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wlr_log(WLR_ERROR,
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"PRIME export not supported on primary GPU");
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return false;
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}
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}
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2017-09-30 11:22:26 +02:00
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if (drmSetClientCap(drm->fd, DRM_CLIENT_CAP_UNIVERSAL_PLANES, 1)) {
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2018-07-09 23:49:54 +02:00
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wlr_log(WLR_ERROR, "DRM universal planes unsupported");
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2017-08-05 08:15:39 +02:00
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return false;
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}
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2019-06-26 17:14:31 +02:00
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if (drmGetCap(drm->fd, DRM_CAP_CRTC_IN_VBLANK_EVENT, &cap) || !cap) {
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wlr_log(WLR_ERROR, "DRM_CRTC_IN_VBLANK_EVENT unsupported");
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return false;
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}
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2018-05-03 14:05:47 +02:00
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const char *no_atomic = getenv("WLR_DRM_NO_ATOMIC");
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if (no_atomic && strcmp(no_atomic, "1") == 0) {
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2018-10-01 22:44:33 +02:00
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wlr_log(WLR_DEBUG,
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"WLR_DRM_NO_ATOMIC set, forcing legacy DRM interface");
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2017-10-02 10:44:33 +02:00
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drm->iface = &legacy_iface;
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2017-09-30 11:22:26 +02:00
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} else if (drmSetClientCap(drm->fd, DRM_CLIENT_CAP_ATOMIC, 1)) {
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2018-10-01 22:44:33 +02:00
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wlr_log(WLR_DEBUG,
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"Atomic modesetting unsupported, using legacy DRM interface");
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2017-10-02 10:44:33 +02:00
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drm->iface = &legacy_iface;
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2017-08-09 10:43:01 +02:00
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} else {
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2018-07-09 23:49:54 +02:00
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wlr_log(WLR_DEBUG, "Using atomic DRM interface");
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2017-10-02 10:44:33 +02:00
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drm->iface = &atomic_iface;
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2017-08-05 08:15:39 +02:00
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}
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2018-10-01 22:44:33 +02:00
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int ret = drmGetCap(drm->fd, DRM_CAP_TIMESTAMP_MONOTONIC, &cap);
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drm->clock = (ret == 0 && cap == 1) ? CLOCK_MONOTONIC : CLOCK_REALTIME;
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2019-05-26 16:38:35 +02:00
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ret = drmGetCap(drm->fd, DRM_CAP_ADDFB2_MODIFIERS, &cap);
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drm->addfb2_modifiers = ret == 0 && cap == 1;
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2017-08-05 08:15:39 +02:00
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return true;
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}
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2019-06-21 08:06:21 +02:00
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static bool add_plane(struct wlr_drm_backend *drm,
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struct wlr_drm_crtc *crtc, drmModePlane *drm_plane,
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uint32_t type, union wlr_drm_plane_props *props) {
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assert(!(type == DRM_PLANE_TYPE_PRIMARY && crtc->primary));
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2017-07-20 10:51:59 +02:00
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2019-06-21 08:06:21 +02:00
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if (type == DRM_PLANE_TYPE_CURSOR && crtc->cursor) {
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return true;
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}
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struct wlr_drm_plane *p = calloc(1, sizeof(*p));
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if (!p) {
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wlr_log_errno(WLR_ERROR, "Allocation failed");
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return false;
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}
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p->type = type;
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p->id = drm_plane->plane_id;
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p->props = *props;
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2019-08-14 20:53:10 +02:00
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for (size_t j = 0; j < drm_plane->count_formats; ++j) {
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wlr_drm_format_set_add(&p->formats, drm_plane->formats[j],
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DRM_FORMAT_MOD_INVALID);
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}
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2019-06-21 08:06:21 +02:00
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// Choose an RGB format for the plane
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uint32_t rgb_format = DRM_FORMAT_INVALID;
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for (size_t j = 0; j < drm_plane->count_formats; ++j) {
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uint32_t fmt = drm_plane->formats[j];
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if (fmt == DRM_FORMAT_ARGB8888) {
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// Prefer formats with alpha channel
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rgb_format = fmt;
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break;
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} else if (fmt == DRM_FORMAT_XRGB8888) {
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rgb_format = fmt;
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}
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}
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p->drm_format = rgb_format;
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if (p->props.in_formats) {
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uint64_t blob_id;
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if (!get_drm_prop(drm->fd, p->id, p->props.in_formats, &blob_id)) {
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wlr_log(WLR_ERROR, "Failed to read IN_FORMATS property");
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goto error;
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}
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drmModePropertyBlobRes *blob = drmModeGetPropertyBlob(drm->fd, blob_id);
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if (!blob) {
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wlr_log(WLR_ERROR, "Failed to read IN_FORMATS blob");
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goto error;
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}
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struct drm_format_modifier_blob *data = blob->data;
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uint32_t *fmts = (uint32_t *)((char *)data + data->formats_offset);
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struct drm_format_modifier *mods = (struct drm_format_modifier *)
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((char *)data + data->modifiers_offset);
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for (uint32_t i = 0; i < data->count_modifiers; ++i) {
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for (int j = 0; j < 64; ++j) {
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if (mods[i].formats & ((uint64_t)1 << j)) {
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wlr_drm_format_set_add(&p->formats,
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fmts[j + mods[i].offset], mods[i].modifier);
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}
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}
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}
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drmModeFreePropertyBlob(blob);
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}
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switch (type) {
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case DRM_PLANE_TYPE_PRIMARY:
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crtc->primary = p;
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break;
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case DRM_PLANE_TYPE_CURSOR:
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crtc->cursor = p;
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break;
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default:
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abort();
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}
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return true;
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error:
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free(p);
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return false;
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2017-07-20 10:51:59 +02:00
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}
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2017-09-30 11:22:26 +02:00
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static bool init_planes(struct wlr_drm_backend *drm) {
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drmModePlaneRes *plane_res = drmModeGetPlaneResources(drm->fd);
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2017-07-20 10:51:59 +02:00
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if (!plane_res) {
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2018-07-09 23:49:54 +02:00
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wlr_log_errno(WLR_ERROR, "Failed to get DRM plane resources");
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2017-07-20 10:51:59 +02:00
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return false;
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}
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2018-07-09 23:49:54 +02:00
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wlr_log(WLR_INFO, "Found %"PRIu32" DRM planes", plane_res->count_planes);
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2017-07-20 10:51:59 +02:00
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2019-06-21 08:06:21 +02:00
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for (uint32_t i = 0; i < plane_res->count_planes; ++i) {
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uint32_t id = plane_res->planes[i];
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2017-07-20 10:51:59 +02:00
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2019-06-21 08:06:21 +02:00
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drmModePlane *plane = drmModeGetPlane(drm->fd, id);
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2017-07-20 10:51:59 +02:00
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if (!plane) {
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2018-07-09 23:49:54 +02:00
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wlr_log_errno(WLR_ERROR, "Failed to get DRM plane");
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2019-06-21 08:06:21 +02:00
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goto error;
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2017-07-20 10:51:59 +02:00
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}
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2019-06-21 08:06:21 +02:00
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union wlr_drm_plane_props props = {0};
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if (!get_drm_plane_props(drm->fd, id, &props)) {
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drmModeFreePlane(plane);
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goto error;
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}
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2017-07-20 10:51:59 +02:00
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2019-01-29 12:04:12 +01:00
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uint64_t type;
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2019-06-21 08:06:21 +02:00
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if (!get_drm_prop(drm->fd, id, props.type, &type)) {
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2017-07-20 10:51:59 +02:00
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drmModeFreePlane(plane);
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2019-06-21 08:06:21 +02:00
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goto error;
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2017-07-20 10:51:59 +02:00
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}
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2019-06-21 08:06:21 +02:00
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/*
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* This is a very naive implementation of the plane matching
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* logic. Primary and cursor planes should only work on a
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* single CRTC, and this should be perfectly adequate, but
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* overlay planes can potentially work with multiple CRTCs,
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2019-11-23 13:04:06 +01:00
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* meaning this could return inefficient/skewed results.
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2019-06-21 08:06:21 +02:00
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*
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* However, we don't really care about overlay planes, as we
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* don't support them yet. We only bother to keep basic
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* tracking of them for DRM lease clients.
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*
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* possible_crtcs is a bitmask of crtcs, where each bit is an
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* index into drmModeRes.crtcs. So if bit 0 is set (ffs starts
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* counting from 1), crtc 0 is possible.
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*/
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int crtc_bit = ffs(plane->possible_crtcs) - 1;
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// This would be a kernel bug
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assert(crtc_bit >= 0 && (size_t)crtc_bit < drm->num_crtcs);
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struct wlr_drm_crtc *crtc = &drm->crtcs[crtc_bit];
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if (type == DRM_PLANE_TYPE_OVERLAY) {
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uint32_t *tmp = realloc(crtc->overlays,
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sizeof(*crtc->overlays) * (crtc->num_overlays + 1));
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if (tmp) {
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crtc->overlays = tmp;
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crtc->overlays[crtc->num_overlays++] = id;
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2019-01-29 12:04:12 +01:00
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}
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drmModeFreePlane(plane);
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2019-06-21 08:06:21 +02:00
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continue;
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2019-01-29 12:04:12 +01:00
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}
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2019-04-09 22:36:35 +02:00
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2019-06-21 08:06:21 +02:00
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if (!add_plane(drm, crtc, plane, type, &props)) {
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drmModeFreePlane(plane);
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goto error;
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2019-04-09 22:36:35 +02:00
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}
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2017-07-20 10:51:59 +02:00
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drmModeFreePlane(plane);
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}
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2017-08-12 00:02:04 +02:00
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drmModeFreePlaneResources(plane_res);
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2017-07-20 10:51:59 +02:00
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return true;
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2019-06-21 08:06:21 +02:00
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error:
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2017-07-20 10:51:59 +02:00
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drmModeFreePlaneResources(plane_res);
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return false;
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}
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2018-04-26 00:24:58 +02:00
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bool init_drm_resources(struct wlr_drm_backend *drm) {
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2017-09-30 11:22:26 +02:00
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drmModeRes *res = drmModeGetResources(drm->fd);
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2017-07-20 10:51:59 +02:00
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if (!res) {
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2018-07-09 23:49:54 +02:00
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wlr_log_errno(WLR_ERROR, "Failed to get DRM resources");
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2017-07-20 10:51:59 +02:00
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return false;
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}
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2018-07-09 23:49:54 +02:00
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wlr_log(WLR_INFO, "Found %d DRM CRTCs", res->count_crtcs);
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2017-07-20 10:51:59 +02:00
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2017-09-30 11:22:26 +02:00
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drm->num_crtcs = res->count_crtcs;
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2018-10-07 12:59:00 +02:00
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if (drm->num_crtcs == 0) {
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drmModeFreeResources(res);
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return true;
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}
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2017-09-30 11:22:26 +02:00
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drm->crtcs = calloc(drm->num_crtcs, sizeof(drm->crtcs[0]));
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if (!drm->crtcs) {
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2018-07-09 23:49:54 +02:00
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wlr_log_errno(WLR_ERROR, "Allocation failed");
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2017-07-20 10:51:59 +02:00
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goto error_res;
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}
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2017-09-30 11:22:26 +02:00
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for (size_t i = 0; i < drm->num_crtcs; ++i) {
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struct wlr_drm_crtc *crtc = &drm->crtcs[i];
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2017-07-20 10:51:59 +02:00
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crtc->id = res->crtcs[i];
|
2018-02-04 21:03:44 +01:00
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crtc->legacy_crtc = drmModeGetCrtc(drm->fd, crtc->id);
|
2018-04-26 00:24:58 +02:00
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get_drm_crtc_props(drm->fd, crtc->id, &crtc->props);
|
2017-07-20 10:51:59 +02:00
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}
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2017-09-30 11:22:26 +02:00
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if (!init_planes(drm)) {
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2017-07-20 10:51:59 +02:00
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goto error_crtcs;
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}
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drmModeFreeResources(res);
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return true;
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error_crtcs:
|
2017-09-30 11:22:26 +02:00
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free(drm->crtcs);
|
2017-07-20 10:51:59 +02:00
|
|
|
error_res:
|
|
|
|
drmModeFreeResources(res);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-04-26 00:24:58 +02:00
|
|
|
void finish_drm_resources(struct wlr_drm_backend *drm) {
|
2017-09-30 11:22:26 +02:00
|
|
|
if (!drm) {
|
2017-08-05 09:49:34 +02:00
|
|
|
return;
|
2017-08-07 00:15:05 +02:00
|
|
|
}
|
2017-09-30 11:22:26 +02:00
|
|
|
|
|
|
|
for (size_t i = 0; i < drm->num_crtcs; ++i) {
|
|
|
|
struct wlr_drm_crtc *crtc = &drm->crtcs[i];
|
2019-06-21 08:06:21 +02:00
|
|
|
|
2017-08-09 10:43:01 +02:00
|
|
|
drmModeAtomicFree(crtc->atomic);
|
2018-02-04 21:03:44 +01:00
|
|
|
drmModeFreeCrtc(crtc->legacy_crtc);
|
2019-06-21 08:06:21 +02:00
|
|
|
|
2017-08-09 10:43:01 +02:00
|
|
|
if (crtc->mode_id) {
|
2017-09-30 11:22:26 +02:00
|
|
|
drmModeDestroyPropertyBlob(drm->fd, crtc->mode_id);
|
2017-08-09 10:43:01 +02:00
|
|
|
}
|
2018-02-01 20:27:35 +01:00
|
|
|
if (crtc->gamma_lut) {
|
|
|
|
drmModeDestroyPropertyBlob(drm->fd, crtc->gamma_lut);
|
|
|
|
}
|
2019-06-21 08:06:21 +02:00
|
|
|
|
2018-10-03 10:53:35 +02:00
|
|
|
free(crtc->gamma_table);
|
2019-06-21 08:06:21 +02:00
|
|
|
|
|
|
|
if (crtc->primary) {
|
|
|
|
wlr_drm_format_set_finish(&crtc->primary->formats);
|
|
|
|
free(crtc->primary);
|
|
|
|
}
|
|
|
|
if (crtc->cursor) {
|
|
|
|
wlr_drm_format_set_finish(&crtc->cursor->formats);
|
|
|
|
free(crtc->cursor);
|
|
|
|
}
|
|
|
|
free(crtc->overlays);
|
2017-08-09 10:43:01 +02:00
|
|
|
}
|
2017-10-05 22:01:56 +02:00
|
|
|
|
2017-09-30 11:22:26 +02:00
|
|
|
free(drm->crtcs);
|
2017-08-05 09:49:34 +02:00
|
|
|
}
|
|
|
|
|
2018-09-17 22:25:20 +02:00
|
|
|
static struct wlr_drm_connector *get_drm_connector_from_output(
|
|
|
|
struct wlr_output *wlr_output) {
|
|
|
|
assert(wlr_output_is_drm(wlr_output));
|
|
|
|
return (struct wlr_drm_connector *)wlr_output;
|
|
|
|
}
|
|
|
|
|
2019-04-23 18:26:21 +02:00
|
|
|
static bool drm_connector_attach_render(struct wlr_output *output,
|
2018-01-21 00:06:35 +01:00
|
|
|
int *buffer_age) {
|
2018-09-17 22:25:20 +02:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
2020-02-08 07:02:31 +01:00
|
|
|
return drm_surface_make_current(&conn->crtc->primary->surf, buffer_age);
|
|
|
|
}
|
|
|
|
|
2020-05-07 17:11:32 +02:00
|
|
|
static bool drm_crtc_page_flip(struct wlr_drm_connector *conn) {
|
|
|
|
struct wlr_drm_backend *drm =
|
|
|
|
get_drm_backend_from_backend(conn->output.backend);
|
2020-02-08 07:02:31 +01:00
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
|
|
|
|
|
|
|
if (conn->pageflip_pending) {
|
2020-05-01 16:09:34 +02:00
|
|
|
wlr_log(WLR_ERROR, "Failed to page-flip output '%s': "
|
|
|
|
"a page-flip is already pending", conn->output.name);
|
2020-02-08 07:02:31 +01:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2020-05-07 17:11:32 +02:00
|
|
|
bool ok = drm->iface->crtc_pageflip(drm, conn);
|
|
|
|
|
|
|
|
crtc->pending = 0;
|
|
|
|
|
|
|
|
if (!ok) {
|
2020-02-08 07:02:31 +01:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
conn->pageflip_pending = true;
|
|
|
|
drm_fb_move(&crtc->primary->queued_fb, &crtc->primary->pending_fb);
|
|
|
|
wlr_output_update_enabled(&conn->output, true);
|
|
|
|
return true;
|
2017-05-03 12:40:19 +02:00
|
|
|
}
|
|
|
|
|
2020-04-02 14:12:26 +02:00
|
|
|
static uint32_t strip_alpha_channel(uint32_t format) {
|
|
|
|
switch (format) {
|
|
|
|
case DRM_FORMAT_ARGB8888:
|
|
|
|
return DRM_FORMAT_XRGB8888;
|
|
|
|
default:
|
|
|
|
return DRM_FORMAT_INVALID;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool test_buffer(struct wlr_drm_connector *conn,
|
|
|
|
struct wlr_buffer *wlr_buffer) {
|
|
|
|
struct wlr_output *output = &conn->output;
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
|
|
|
|
|
|
|
if (!drm->session->active) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2020-04-27 11:09:48 +02:00
|
|
|
/* Legacy never gets to have nice things. But I doubt this would ever work,
|
|
|
|
* and there is no reliable way to try, without risking messing up the
|
|
|
|
* modesetting state. */
|
|
|
|
if (drm->iface == &legacy_iface) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2020-04-02 14:12:26 +02:00
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
|
|
|
if (!crtc) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct wlr_dmabuf_attributes attribs;
|
|
|
|
if (!wlr_buffer_get_dmabuf(wlr_buffer, &attribs)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (attribs.flags != 0) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!wlr_drm_format_set_has(&crtc->primary->formats,
|
|
|
|
attribs.format, attribs.modifier)) {
|
|
|
|
// The format isn't supported by the plane. Try stripping the alpha
|
|
|
|
// channel, if any.
|
|
|
|
uint32_t format = strip_alpha_channel(attribs.format);
|
|
|
|
if (format != DRM_FORMAT_INVALID && wlr_drm_format_set_has(
|
|
|
|
&crtc->primary->formats, format, attribs.modifier)) {
|
|
|
|
attribs.format = format;
|
|
|
|
} else {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2020-04-02 12:41:19 +02:00
|
|
|
static bool drm_connector_test(struct wlr_output *output) {
|
2020-04-02 14:12:26 +02:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
|
|
|
|
if ((output->pending.committed & WLR_OUTPUT_STATE_BUFFER) &&
|
|
|
|
output->pending.buffer_type == WLR_OUTPUT_STATE_BUFFER_SCANOUT) {
|
|
|
|
if (!test_buffer(conn, output->pending.buffer)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-04-02 12:41:19 +02:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-08-16 18:41:56 +02:00
|
|
|
static bool drm_connector_commit_buffer(struct wlr_output *output) {
|
2018-09-17 22:25:20 +02:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2017-09-30 11:22:26 +02:00
|
|
|
|
2017-09-30 12:31:08 +02:00
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
2018-01-21 21:37:23 +01:00
|
|
|
if (!crtc) {
|
2018-01-21 22:16:55 +01:00
|
|
|
return false;
|
2018-01-21 21:37:23 +01:00
|
|
|
}
|
2017-08-05 07:27:59 +02:00
|
|
|
struct wlr_drm_plane *plane = crtc->primary;
|
2017-05-03 12:40:19 +02:00
|
|
|
|
2019-04-29 22:25:47 +02:00
|
|
|
assert(output->pending.committed & WLR_OUTPUT_STATE_BUFFER);
|
|
|
|
switch (output->pending.buffer_type) {
|
|
|
|
case WLR_OUTPUT_STATE_BUFFER_RENDER:
|
2020-02-08 07:02:31 +01:00
|
|
|
if (!drm_fb_lock_surface(&plane->pending_fb, &plane->surf)) {
|
|
|
|
wlr_log(WLR_ERROR, "drm_fb_lock_surface failed");
|
2019-04-29 22:25:47 +02:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
2020-04-02 14:12:26 +02:00
|
|
|
case WLR_OUTPUT_STATE_BUFFER_SCANOUT:;
|
2020-02-08 07:02:31 +01:00
|
|
|
struct wlr_buffer *buffer = output->pending.buffer;
|
|
|
|
if (!test_buffer(conn, output->pending.buffer)) {
|
2019-04-29 22:25:47 +02:00
|
|
|
return false;
|
|
|
|
}
|
2020-02-08 07:02:31 +01:00
|
|
|
if (!drm_fb_import_wlr(&plane->pending_fb, &drm->renderer, buffer,
|
|
|
|
&crtc->primary->formats)) {
|
2019-04-29 22:25:47 +02:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
2017-10-01 08:22:47 +02:00
|
|
|
}
|
2017-09-23 08:27:14 +02:00
|
|
|
|
2020-05-07 17:11:32 +02:00
|
|
|
if (!drm_crtc_page_flip(conn)) {
|
2020-02-08 07:02:31 +01:00
|
|
|
drm_fb_clear(&plane->pending_fb);
|
2018-01-28 23:33:38 +01:00
|
|
|
return false;
|
2017-09-23 08:27:14 +02:00
|
|
|
}
|
2018-01-21 00:06:35 +01:00
|
|
|
|
|
|
|
return true;
|
2017-06-21 03:31:29 +02:00
|
|
|
}
|
|
|
|
|
2020-01-10 16:04:19 +01:00
|
|
|
static void drm_connector_enable_adaptive_sync(struct wlr_output *output,
|
|
|
|
bool enabled) {
|
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
|
|
|
|
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
|
|
|
if (!crtc) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
uint64_t vrr_capable;
|
|
|
|
if (conn->props.vrr_capable == 0 ||
|
|
|
|
!get_drm_prop(drm->fd, conn->id, conn->props.vrr_capable,
|
|
|
|
&vrr_capable) || !vrr_capable) {
|
|
|
|
wlr_log(WLR_DEBUG, "Failed to enable adaptive sync: "
|
|
|
|
"connector '%s' doesn't support VRR", output->name);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (crtc->props.vrr_enabled == 0) {
|
|
|
|
wlr_log(WLR_DEBUG, "Failed to enable adaptive sync: "
|
|
|
|
"CRTC %"PRIu32" doesn't support VRR", crtc->id);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (drmModeObjectSetProperty(drm->fd, crtc->id, DRM_MODE_OBJECT_CRTC,
|
|
|
|
crtc->props.vrr_enabled, enabled) != 0) {
|
|
|
|
wlr_log_errno(WLR_ERROR, "drmModeObjectSetProperty(VRR_ENABLED) failed");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
output->adaptive_sync_status = enabled ? WLR_OUTPUT_ADAPTIVE_SYNC_ENABLED :
|
|
|
|
WLR_OUTPUT_ADAPTIVE_SYNC_DISABLED;
|
|
|
|
wlr_log(WLR_DEBUG, "VRR %s on connector '%s'",
|
|
|
|
enabled ? "enabled" : "disabled", output->name);
|
|
|
|
}
|
|
|
|
|
2019-08-16 18:41:56 +02:00
|
|
|
static bool drm_connector_set_custom_mode(struct wlr_output *output,
|
|
|
|
int32_t width, int32_t height, int32_t refresh);
|
|
|
|
|
|
|
|
static bool drm_connector_commit(struct wlr_output *output) {
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
|
|
|
|
2020-04-02 12:41:19 +02:00
|
|
|
if (!drm_connector_test(output)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2019-08-16 18:41:56 +02:00
|
|
|
if (!drm->session->active) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (output->pending.committed & WLR_OUTPUT_STATE_MODE) {
|
|
|
|
switch (output->pending.mode_type) {
|
|
|
|
case WLR_OUTPUT_STATE_MODE_FIXED:
|
|
|
|
if (!drm_connector_set_mode(output, output->pending.mode)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case WLR_OUTPUT_STATE_MODE_CUSTOM:
|
|
|
|
if (!drm_connector_set_custom_mode(output,
|
|
|
|
output->pending.custom_mode.width,
|
|
|
|
output->pending.custom_mode.height,
|
|
|
|
output->pending.custom_mode.refresh)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-12-27 12:43:49 +01:00
|
|
|
if (output->pending.committed & WLR_OUTPUT_STATE_ENABLED) {
|
|
|
|
if (!enable_drm_connector(output, output->pending.enabled)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-01-10 16:04:19 +01:00
|
|
|
if (output->pending.committed & WLR_OUTPUT_STATE_ADAPTIVE_SYNC_ENABLED) {
|
|
|
|
drm_connector_enable_adaptive_sync(output,
|
|
|
|
output->pending.adaptive_sync_enabled);
|
|
|
|
}
|
|
|
|
|
2019-12-27 11:59:15 +01:00
|
|
|
// TODO: support modesetting with a buffer
|
|
|
|
if (output->pending.committed & WLR_OUTPUT_STATE_BUFFER &&
|
|
|
|
!(output->pending.committed & WLR_OUTPUT_STATE_MODE)) {
|
2019-08-16 18:41:56 +02:00
|
|
|
if (!drm_connector_commit_buffer(output)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-04-06 11:43:58 +02:00
|
|
|
wlr_egl_make_current(&drm->renderer.egl, EGL_NO_SURFACE, NULL);
|
|
|
|
|
2019-08-16 18:41:56 +02:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2020-04-06 11:53:20 +02:00
|
|
|
static void drm_connector_rollback(struct wlr_output *output) {
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
|
|
|
wlr_egl_make_current(&drm->renderer.egl, EGL_NO_SURFACE, NULL);
|
|
|
|
}
|
|
|
|
|
2018-10-03 10:36:33 +02:00
|
|
|
static void fill_empty_gamma_table(size_t size,
|
2018-07-22 18:37:01 +02:00
|
|
|
uint16_t *r, uint16_t *g, uint16_t *b) {
|
2020-04-02 12:41:19 +02:00
|
|
|
assert(0xFFFF < UINT64_MAX / (size - 1));
|
2018-07-22 18:37:01 +02:00
|
|
|
for (uint32_t i = 0; i < size; ++i) {
|
2020-03-15 18:41:12 +01:00
|
|
|
uint16_t val = (uint64_t)0xffff * i / (size - 1);
|
2018-07-22 18:37:01 +02:00
|
|
|
r[i] = g[i] = b[i] = val;
|
2018-02-04 21:50:52 +01:00
|
|
|
}
|
2017-09-06 18:53:08 +02:00
|
|
|
}
|
|
|
|
|
2018-10-03 10:36:33 +02:00
|
|
|
static size_t drm_connector_get_gamma_size(struct wlr_output *output) {
|
2018-09-17 22:25:20 +02:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2018-02-04 21:50:52 +01:00
|
|
|
|
|
|
|
if (conn->crtc) {
|
|
|
|
return drm->iface->crtc_get_gamma_size(drm, conn->crtc);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2017-09-06 18:53:08 +02:00
|
|
|
}
|
|
|
|
|
2018-10-03 10:53:35 +02:00
|
|
|
bool set_drm_connector_gamma(struct wlr_output *output, size_t size,
|
2018-10-03 10:36:33 +02:00
|
|
|
const uint16_t *r, const uint16_t *g, const uint16_t *b) {
|
2018-09-17 22:25:20 +02:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
2018-07-22 18:37:01 +02:00
|
|
|
|
|
|
|
if (!conn->crtc) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2018-10-03 10:36:33 +02:00
|
|
|
bool reset = false;
|
2018-07-22 18:37:01 +02:00
|
|
|
if (size == 0) {
|
2018-10-03 10:36:33 +02:00
|
|
|
reset = true;
|
2018-07-22 18:37:01 +02:00
|
|
|
size = drm_connector_get_gamma_size(output);
|
2018-10-03 10:36:33 +02:00
|
|
|
if (size == 0) {
|
2018-07-22 18:37:01 +02:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-10-03 10:36:33 +02:00
|
|
|
uint16_t *gamma_table = malloc(3 * size * sizeof(uint16_t));
|
|
|
|
if (gamma_table == NULL) {
|
|
|
|
wlr_log(WLR_ERROR, "Failed to allocate gamma table");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
uint16_t *_r = gamma_table;
|
|
|
|
uint16_t *_g = gamma_table + size;
|
|
|
|
uint16_t *_b = gamma_table + 2 * size;
|
|
|
|
|
|
|
|
if (reset) {
|
|
|
|
fill_empty_gamma_table(size, _r, _g, _b);
|
|
|
|
} else {
|
|
|
|
memcpy(_r, r, size * sizeof(uint16_t));
|
|
|
|
memcpy(_g, g, size * sizeof(uint16_t));
|
|
|
|
memcpy(_b, b, size * sizeof(uint16_t));
|
|
|
|
}
|
|
|
|
|
2020-05-07 17:50:40 +02:00
|
|
|
conn->crtc->pending |= WLR_DRM_CRTC_GAMMA_LUT;
|
|
|
|
free(conn->crtc->gamma_table);
|
|
|
|
conn->crtc->gamma_table = gamma_table;
|
|
|
|
conn->crtc->gamma_table_size = size;
|
2018-10-03 10:53:35 +02:00
|
|
|
|
2020-05-07 17:50:40 +02:00
|
|
|
wlr_output_update_needs_frame(output);
|
|
|
|
return true; // will be applied on next page-flip
|
2018-07-22 18:37:01 +02:00
|
|
|
}
|
|
|
|
|
2018-05-21 19:50:51 +02:00
|
|
|
static bool drm_connector_export_dmabuf(struct wlr_output *output,
|
2018-05-31 13:33:27 +02:00
|
|
|
struct wlr_dmabuf_attributes *attribs) {
|
2018-09-17 22:25:20 +02:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2020-02-08 07:02:31 +01:00
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
2018-05-21 19:50:51 +02:00
|
|
|
|
|
|
|
if (!drm->session->active) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!crtc) {
|
|
|
|
return false;
|
|
|
|
}
|
2020-02-08 07:02:31 +01:00
|
|
|
|
2018-05-21 19:50:51 +02:00
|
|
|
struct wlr_drm_plane *plane = crtc->primary;
|
|
|
|
|
2020-02-08 07:02:31 +01:00
|
|
|
if (plane->current_fb.type == WLR_DRM_FB_TYPE_NONE) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return export_drm_bo(plane->current_fb.bo, attribs);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct wlr_drm_fb *plane_get_next_fb(struct wlr_drm_plane *plane) {
|
|
|
|
if (plane->pending_fb.type != WLR_DRM_FB_TYPE_NONE) {
|
|
|
|
return &plane->pending_fb;
|
|
|
|
}
|
|
|
|
if (plane->queued_fb.type != WLR_DRM_FB_TYPE_NONE) {
|
|
|
|
return &plane->queued_fb;
|
|
|
|
}
|
|
|
|
return &plane->current_fb;
|
2018-05-21 19:50:51 +02:00
|
|
|
}
|
|
|
|
|
2020-05-07 17:11:32 +02:00
|
|
|
static bool drm_connector_pageflip_renderer(struct wlr_drm_connector *conn) {
|
2017-09-30 12:31:08 +02:00
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
2018-01-21 21:37:23 +01:00
|
|
|
if (!crtc) {
|
2019-10-22 18:41:47 +02:00
|
|
|
wlr_log(WLR_ERROR, "Page-flip failed on connector '%s': no CRTC",
|
|
|
|
conn->output.name);
|
|
|
|
return false;
|
2018-01-21 21:37:23 +01:00
|
|
|
}
|
2020-02-08 07:02:31 +01:00
|
|
|
|
|
|
|
// drm_crtc_page_flip expects a FB to be available
|
2017-08-05 07:27:59 +02:00
|
|
|
struct wlr_drm_plane *plane = crtc->primary;
|
2020-02-08 07:02:31 +01:00
|
|
|
if (plane_get_next_fb(plane)->type == WLR_DRM_FB_TYPE_NONE) {
|
|
|
|
drm_surface_render_black_frame(&plane->surf);
|
|
|
|
if (!drm_fb_lock_surface(&plane->pending_fb, &plane->surf)) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
2017-05-01 05:20:48 +02:00
|
|
|
|
2020-05-07 17:11:32 +02:00
|
|
|
return drm_crtc_page_flip(conn);
|
2019-10-22 18:41:47 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void drm_connector_start_renderer(struct wlr_drm_connector *conn) {
|
2020-05-07 17:11:32 +02:00
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
|
|
|
|
2019-10-22 18:41:47 +02:00
|
|
|
if (conn->state != WLR_DRM_CONN_CONNECTED) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
wlr_log(WLR_DEBUG, "Starting renderer on output '%s'", conn->output.name);
|
2017-05-01 05:20:48 +02:00
|
|
|
|
2017-09-30 12:31:08 +02:00
|
|
|
struct wlr_drm_mode *mode = (struct wlr_drm_mode *)conn->output.current_mode;
|
2020-05-07 17:11:32 +02:00
|
|
|
memcpy(&crtc->mode, &mode->drm_mode, sizeof(drmModeModeInfo));
|
|
|
|
crtc->pending |= WLR_DRM_CRTC_MODE;
|
|
|
|
|
|
|
|
if (!drm_connector_pageflip_renderer(conn)) {
|
2017-09-30 12:31:08 +02:00
|
|
|
wl_event_source_timer_update(conn->retry_pageflip,
|
2018-01-19 23:35:23 +01:00
|
|
|
1000000.0f / conn->output.current_mode->refresh);
|
2017-09-23 08:27:14 +02:00
|
|
|
}
|
2017-05-14 02:48:47 +02:00
|
|
|
}
|
|
|
|
|
2019-10-22 18:41:47 +02:00
|
|
|
static bool drm_connector_init_renderer(struct wlr_drm_connector *conn,
|
|
|
|
struct wlr_drm_mode *mode) {
|
|
|
|
struct wlr_drm_backend *drm =
|
|
|
|
get_drm_backend_from_backend(conn->output.backend);
|
|
|
|
|
|
|
|
if (conn->state != WLR_DRM_CONN_CONNECTED &&
|
|
|
|
conn->state != WLR_DRM_CONN_NEEDS_MODESET) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
wlr_log(WLR_DEBUG, "Initializing renderer on connector '%s'",
|
|
|
|
conn->output.name);
|
|
|
|
|
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
|
|
|
if (!crtc) {
|
|
|
|
wlr_log(WLR_ERROR, "Failed to initialize renderer on connector '%s': "
|
|
|
|
"no CRTC", conn->output.name);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
struct wlr_drm_plane *plane = crtc->primary;
|
|
|
|
|
2020-05-07 17:11:32 +02:00
|
|
|
crtc->pending |= WLR_DRM_CRTC_MODE;
|
|
|
|
memcpy(&crtc->mode, &mode->drm_mode, sizeof(drmModeModeInfo));
|
|
|
|
|
2019-10-22 18:41:47 +02:00
|
|
|
int width = mode->wlr_mode.width;
|
|
|
|
int height = mode->wlr_mode.height;
|
|
|
|
uint32_t format = drm->renderer.gbm_format;
|
|
|
|
|
2020-01-24 19:31:39 +01:00
|
|
|
bool modifiers = true;
|
|
|
|
const char *no_modifiers = getenv("WLR_DRM_NO_MODIFIERS");
|
|
|
|
if (no_modifiers != NULL && strcmp(no_modifiers, "1") == 0) {
|
|
|
|
wlr_log(WLR_DEBUG,
|
|
|
|
"WLR_DRM_NO_MODIFIERS set, initializing planes without modifiers");
|
|
|
|
modifiers = false;
|
|
|
|
}
|
|
|
|
|
2020-02-08 07:02:31 +01:00
|
|
|
if (!drm_plane_init_surface(plane, drm, width, height, format, 0, modifiers) ||
|
2020-05-07 17:11:32 +02:00
|
|
|
!drm_connector_pageflip_renderer(conn)) {
|
2020-01-24 19:31:39 +01:00
|
|
|
if (!modifiers) {
|
|
|
|
wlr_log(WLR_ERROR, "Failed to initialize renderer "
|
|
|
|
"on connector '%s': initial page-flip failed",
|
|
|
|
conn->output.name);
|
|
|
|
return false;
|
|
|
|
}
|
2020-01-24 19:53:51 +01:00
|
|
|
|
|
|
|
// If page-flipping with modifiers enabled doesn't work, retry without
|
|
|
|
// modifiers
|
2020-01-24 19:31:39 +01:00
|
|
|
wlr_log(WLR_INFO, "Page-flip failed with primary FB modifiers enabled, "
|
|
|
|
"retrying without modifiers");
|
|
|
|
modifiers = false;
|
|
|
|
|
2020-02-08 07:02:31 +01:00
|
|
|
if (!drm_plane_init_surface(plane, drm, width, height, format,
|
|
|
|
0, modifiers)) {
|
2019-10-22 18:41:47 +02:00
|
|
|
return false;
|
|
|
|
}
|
2020-05-07 17:11:32 +02:00
|
|
|
if (!drm_connector_pageflip_renderer(conn)) {
|
2019-10-22 18:41:47 +02:00
|
|
|
wlr_log(WLR_ERROR, "Failed to initialize renderer "
|
|
|
|
"on connector '%s': initial page-flip failed",
|
|
|
|
conn->output.name);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
static void realloc_crtcs(struct wlr_drm_backend *drm);
|
2018-09-10 23:35:22 +02:00
|
|
|
|
|
|
|
static void attempt_enable_needs_modeset(struct wlr_drm_backend *drm) {
|
|
|
|
// Try to modeset any output that has a desired mode and a CRTC (ie. was
|
|
|
|
// lacking a CRTC on last modeset)
|
|
|
|
struct wlr_drm_connector *conn;
|
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
|
|
|
if (conn->state == WLR_DRM_CONN_NEEDS_MODESET &&
|
|
|
|
conn->crtc != NULL && conn->desired_mode != NULL &&
|
|
|
|
conn->desired_enabled) {
|
2019-01-19 10:14:01 +01:00
|
|
|
wlr_log(WLR_DEBUG, "Output %s has a desired mode and a CRTC, "
|
|
|
|
"attempting a modeset", conn->output.name);
|
2018-09-10 23:35:22 +02:00
|
|
|
drm_connector_set_mode(&conn->output, conn->desired_mode);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-09-14 18:18:07 +02:00
|
|
|
bool enable_drm_connector(struct wlr_output *output, bool enable) {
|
2018-09-17 22:25:20 +02:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2018-09-01 23:43:16 +02:00
|
|
|
if (conn->state != WLR_DRM_CONN_CONNECTED
|
|
|
|
&& conn->state != WLR_DRM_CONN_NEEDS_MODESET) {
|
2018-09-14 18:18:07 +02:00
|
|
|
return false;
|
2017-06-06 17:48:30 +02:00
|
|
|
}
|
|
|
|
|
2018-09-10 23:35:22 +02:00
|
|
|
conn->desired_enabled = enable;
|
|
|
|
|
|
|
|
if (enable && conn->crtc == NULL) {
|
|
|
|
// Maybe we can steal a CRTC from a disabled output
|
2019-06-21 08:06:21 +02:00
|
|
|
realloc_crtcs(drm);
|
2018-09-10 23:35:22 +02:00
|
|
|
}
|
|
|
|
|
2018-01-07 00:28:21 +01:00
|
|
|
bool ok = drm->iface->conn_enable(drm, conn, enable);
|
|
|
|
if (!ok) {
|
2018-09-14 18:18:07 +02:00
|
|
|
return false;
|
2018-01-07 00:28:21 +01:00
|
|
|
}
|
2017-06-06 17:48:30 +02:00
|
|
|
|
2017-08-09 10:43:01 +02:00
|
|
|
if (enable) {
|
2018-04-21 12:42:18 +02:00
|
|
|
drm_connector_start_renderer(conn);
|
2018-09-10 23:35:22 +02:00
|
|
|
} else {
|
2019-06-21 08:06:21 +02:00
|
|
|
realloc_crtcs(drm);
|
2018-09-10 23:35:22 +02:00
|
|
|
|
|
|
|
attempt_enable_needs_modeset(drm);
|
2017-07-29 12:14:29 +02:00
|
|
|
}
|
2018-01-04 12:46:15 +01:00
|
|
|
|
|
|
|
wlr_output_update_enabled(&conn->output, enable);
|
2018-09-14 18:18:07 +02:00
|
|
|
return true;
|
2017-07-29 12:14:29 +02:00
|
|
|
}
|
|
|
|
|
2018-04-21 12:42:18 +02:00
|
|
|
static void drm_connector_cleanup(struct wlr_drm_connector *conn);
|
|
|
|
|
2019-02-19 16:45:36 +01:00
|
|
|
bool drm_connector_set_mode(struct wlr_output *output,
|
2019-10-22 18:41:47 +02:00
|
|
|
struct wlr_output_mode *wlr_mode) {
|
2018-09-17 22:25:20 +02:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2018-09-10 23:35:22 +02:00
|
|
|
if (conn->crtc == NULL) {
|
|
|
|
// Maybe we can steal a CRTC from a disabled output
|
2019-06-21 08:06:21 +02:00
|
|
|
realloc_crtcs(drm);
|
2018-09-10 23:35:22 +02:00
|
|
|
}
|
2018-09-04 15:09:07 +02:00
|
|
|
if (conn->crtc == NULL) {
|
|
|
|
wlr_log(WLR_ERROR, "Cannot modeset '%s': no CRTC for this connector",
|
|
|
|
conn->output.name);
|
|
|
|
// Save the desired mode for later, when we'll get a proper CRTC
|
2019-10-22 18:41:47 +02:00
|
|
|
conn->desired_mode = wlr_mode;
|
2018-09-04 15:09:07 +02:00
|
|
|
return false;
|
2017-07-31 00:04:34 +02:00
|
|
|
}
|
|
|
|
|
2018-09-04 15:09:07 +02:00
|
|
|
wlr_log(WLR_INFO, "Modesetting '%s' with '%ux%u@%u mHz'",
|
2019-10-22 18:41:47 +02:00
|
|
|
conn->output.name, wlr_mode->width, wlr_mode->height,
|
|
|
|
wlr_mode->refresh);
|
2017-09-30 12:31:08 +02:00
|
|
|
|
2019-10-22 18:41:47 +02:00
|
|
|
struct wlr_drm_mode *mode = (struct wlr_drm_mode *)wlr_mode;
|
|
|
|
if (!drm_connector_init_renderer(conn, mode)) {
|
2018-09-04 15:09:07 +02:00
|
|
|
wlr_log(WLR_ERROR, "Failed to initialize renderer for plane");
|
2018-09-02 01:03:20 +02:00
|
|
|
return false;
|
2018-01-21 21:37:23 +01:00
|
|
|
}
|
2017-05-07 18:26:48 +02:00
|
|
|
|
2017-09-30 12:31:08 +02:00
|
|
|
conn->state = WLR_DRM_CONN_CONNECTED;
|
2018-09-04 15:09:07 +02:00
|
|
|
conn->desired_mode = NULL;
|
2019-10-22 18:41:47 +02:00
|
|
|
wlr_output_update_mode(&conn->output, wlr_mode);
|
2018-09-04 15:09:07 +02:00
|
|
|
wlr_output_update_enabled(&conn->output, true);
|
2018-09-10 23:35:22 +02:00
|
|
|
conn->desired_enabled = true;
|
2018-09-04 15:09:07 +02:00
|
|
|
|
2018-04-18 01:15:25 +02:00
|
|
|
// When switching VTs, the mode is not updated but the buffers become
|
|
|
|
// invalid, so we need to manually damage the output here
|
|
|
|
wlr_output_damage_whole(&conn->output);
|
|
|
|
|
2017-05-07 18:26:48 +02:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2019-10-26 22:35:51 +02:00
|
|
|
static bool drm_connector_set_custom_mode(struct wlr_output *output,
|
|
|
|
int32_t width, int32_t height, int32_t refresh) {
|
|
|
|
drmModeModeInfo mode = {0};
|
|
|
|
generate_cvt_mode(&mode, width, height, (float)refresh / 1000, false, false);
|
|
|
|
mode.type = DRM_MODE_TYPE_USERDEF;
|
|
|
|
|
|
|
|
struct wlr_output_mode *wlr_mode = wlr_drm_connector_add_mode(output, &mode);
|
|
|
|
if (wlr_mode == NULL) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return drm_connector_set_mode(output, wlr_mode);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct wlr_output_mode *wlr_drm_connector_add_mode(struct wlr_output *output,
|
2018-06-28 12:35:55 +02:00
|
|
|
const drmModeModeInfo *modeinfo) {
|
2018-09-17 22:25:20 +02:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
2018-06-28 12:35:55 +02:00
|
|
|
|
|
|
|
if (modeinfo->type != DRM_MODE_TYPE_USERDEF) {
|
2019-10-26 22:35:51 +02:00
|
|
|
return NULL;
|
2018-06-28 12:35:55 +02:00
|
|
|
}
|
|
|
|
|
2018-12-16 11:06:46 +01:00
|
|
|
struct wlr_output_mode *wlr_mode;
|
|
|
|
wl_list_for_each(wlr_mode, &conn->output.modes, link) {
|
|
|
|
struct wlr_drm_mode *mode = (struct wlr_drm_mode *)wlr_mode;
|
|
|
|
if (memcmp(&mode->drm_mode, modeinfo, sizeof(*modeinfo)) == 0) {
|
2019-10-26 22:35:51 +02:00
|
|
|
return wlr_mode;
|
2018-12-16 11:06:46 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-28 12:35:55 +02:00
|
|
|
struct wlr_drm_mode *mode = calloc(1, sizeof(*mode));
|
|
|
|
if (!mode) {
|
2019-10-26 22:35:51 +02:00
|
|
|
return NULL;
|
2018-06-28 12:35:55 +02:00
|
|
|
}
|
|
|
|
memcpy(&mode->drm_mode, modeinfo, sizeof(*modeinfo));
|
|
|
|
|
|
|
|
mode->wlr_mode.width = mode->drm_mode.hdisplay;
|
|
|
|
mode->wlr_mode.height = mode->drm_mode.vdisplay;
|
2018-12-16 11:06:46 +01:00
|
|
|
mode->wlr_mode.refresh = calculate_refresh_rate(modeinfo);
|
2018-06-28 12:35:55 +02:00
|
|
|
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log(WLR_INFO, "Registered custom mode "
|
2018-06-28 12:35:55 +02:00
|
|
|
"%"PRId32"x%"PRId32"@%"PRId32,
|
|
|
|
mode->wlr_mode.width, mode->wlr_mode.height,
|
|
|
|
mode->wlr_mode.refresh);
|
|
|
|
wl_list_insert(&conn->output.modes, &mode->wlr_mode.link);
|
2019-10-26 22:35:51 +02:00
|
|
|
|
|
|
|
return &mode->wlr_mode;
|
2018-06-28 12:35:55 +02:00
|
|
|
}
|
|
|
|
|
2018-04-21 12:42:18 +02:00
|
|
|
static bool drm_connector_set_cursor(struct wlr_output *output,
|
2020-04-10 11:04:21 +02:00
|
|
|
struct wlr_texture *texture, float scale,
|
2018-09-17 22:25:20 +02:00
|
|
|
enum wl_output_transform transform,
|
|
|
|
int32_t hotspot_x, int32_t hotspot_y, bool update_texture) {
|
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
|
|
|
struct wlr_drm_backend *drm = get_drm_backend_from_backend(output->backend);
|
2017-09-30 12:31:08 +02:00
|
|
|
struct wlr_drm_crtc *crtc = conn->crtc;
|
2020-02-08 07:02:31 +01:00
|
|
|
|
2018-01-21 20:57:24 +01:00
|
|
|
if (!crtc) {
|
|
|
|
return false;
|
|
|
|
}
|
2017-06-26 09:32:36 +02:00
|
|
|
|
2018-03-11 11:40:03 +01:00
|
|
|
struct wlr_drm_plane *plane = crtc->cursor;
|
2017-08-06 11:38:40 +02:00
|
|
|
if (!plane) {
|
2018-03-11 11:40:03 +01:00
|
|
|
// We don't have a real cursor plane, so we make a fake one
|
2017-08-06 11:38:40 +02:00
|
|
|
plane = calloc(1, sizeof(*plane));
|
|
|
|
if (!plane) {
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log_errno(WLR_ERROR, "Allocation failed");
|
2017-08-06 11:38:40 +02:00
|
|
|
return false;
|
2017-06-26 09:32:36 +02:00
|
|
|
}
|
2017-08-06 11:38:40 +02:00
|
|
|
crtc->cursor = plane;
|
|
|
|
}
|
2017-06-26 09:32:36 +02:00
|
|
|
|
2017-09-30 09:52:58 +02:00
|
|
|
if (!plane->surf.gbm) {
|
2017-08-06 11:38:40 +02:00
|
|
|
int ret;
|
|
|
|
uint64_t w, h;
|
2017-09-30 11:22:26 +02:00
|
|
|
ret = drmGetCap(drm->fd, DRM_CAP_CURSOR_WIDTH, &w);
|
2017-08-06 11:38:40 +02:00
|
|
|
w = ret ? 64 : w;
|
2017-09-30 11:22:26 +02:00
|
|
|
ret = drmGetCap(drm->fd, DRM_CAP_CURSOR_HEIGHT, &h);
|
2017-08-06 11:38:40 +02:00
|
|
|
h = ret ? 64 : h;
|
|
|
|
|
2020-02-08 07:02:31 +01:00
|
|
|
if (!drm_plane_init_surface(plane, drm, w, h,
|
|
|
|
DRM_FORMAT_ARGB8888, GBM_BO_USE_LINEAR, false)) {
|
|
|
|
wlr_log(WLR_ERROR, "Cannot allocate cursor resources");
|
|
|
|
return false;
|
2017-06-26 09:32:36 +02:00
|
|
|
}
|
2017-06-16 21:38:34 +02:00
|
|
|
}
|
2017-06-26 09:32:36 +02:00
|
|
|
|
2020-02-08 07:02:31 +01:00
|
|
|
float hotspot_proj[9];
|
|
|
|
wlr_matrix_projection(hotspot_proj, plane->surf.width,
|
2018-05-16 15:14:57 +02:00
|
|
|
plane->surf.height, output->transform);
|
|
|
|
|
2018-03-11 11:40:03 +01:00
|
|
|
struct wlr_box hotspot = { .x = hotspot_x, .y = hotspot_y };
|
2019-01-19 10:14:01 +01:00
|
|
|
wlr_box_transform(&hotspot, &hotspot,
|
2018-12-21 19:56:10 +01:00
|
|
|
wlr_output_transform_invert(output->transform),
|
|
|
|
plane->surf.width, plane->surf.height);
|
2017-10-29 18:45:53 +01:00
|
|
|
|
2018-03-11 15:06:06 +01:00
|
|
|
if (plane->cursor_hotspot_x != hotspot.x ||
|
|
|
|
plane->cursor_hotspot_y != hotspot.y) {
|
|
|
|
// Update cursor hotspot
|
|
|
|
conn->cursor_x -= hotspot.x - plane->cursor_hotspot_x;
|
|
|
|
conn->cursor_y -= hotspot.y - plane->cursor_hotspot_y;
|
|
|
|
plane->cursor_hotspot_x = hotspot.x;
|
|
|
|
plane->cursor_hotspot_y = hotspot.y;
|
|
|
|
|
2019-04-23 19:22:42 +02:00
|
|
|
wlr_output_update_needs_frame(output);
|
2018-03-11 15:06:06 +01:00
|
|
|
}
|
|
|
|
|
2018-05-01 22:38:04 +02:00
|
|
|
if (!update_texture) {
|
2018-03-11 15:06:06 +01:00
|
|
|
// Don't update cursor image
|
2017-10-12 09:40:51 +02:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2018-05-01 22:38:04 +02:00
|
|
|
plane->cursor_enabled = false;
|
|
|
|
if (texture != NULL) {
|
|
|
|
int width, height;
|
|
|
|
wlr_texture_get_size(texture, &width, &height);
|
2018-05-09 20:58:18 +02:00
|
|
|
width = width * output->scale / scale;
|
|
|
|
height = height * output->scale / scale;
|
2018-05-01 22:38:04 +02:00
|
|
|
|
|
|
|
if (width > (int)plane->surf.width || height > (int)plane->surf.height) {
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log(WLR_ERROR, "Cursor too large (max %dx%d)",
|
2018-05-01 22:38:04 +02:00
|
|
|
(int)plane->surf.width, (int)plane->surf.height);
|
|
|
|
return false;
|
|
|
|
}
|
2017-08-07 11:07:42 +02:00
|
|
|
|
2020-02-08 07:02:31 +01:00
|
|
|
drm_surface_make_current(&plane->surf, NULL);
|
2017-06-26 07:34:15 +02:00
|
|
|
|
2018-03-20 23:10:42 +01:00
|
|
|
struct wlr_renderer *rend = plane->surf.renderer->wlr_rend;
|
2018-03-24 23:30:28 +01:00
|
|
|
|
2018-05-09 20:58:18 +02:00
|
|
|
struct wlr_box cursor_box = { .width = width, .height = height };
|
|
|
|
|
|
|
|
float matrix[9];
|
2020-02-08 07:02:31 +01:00
|
|
|
wlr_matrix_project_box(matrix, &cursor_box, transform, 0, hotspot_proj);
|
2018-05-09 20:58:18 +02:00
|
|
|
|
2018-03-20 23:10:42 +01:00
|
|
|
wlr_renderer_begin(rend, plane->surf.width, plane->surf.height);
|
|
|
|
wlr_renderer_clear(rend, (float[]){ 0.0, 0.0, 0.0, 0.0 });
|
2018-05-09 20:58:18 +02:00
|
|
|
wlr_render_texture_with_matrix(rend, texture, matrix, 1.0);
|
2018-03-20 23:10:42 +01:00
|
|
|
wlr_renderer_end(rend);
|
2017-08-06 11:38:40 +02:00
|
|
|
|
2020-02-08 07:02:31 +01:00
|
|
|
if (!drm_fb_lock_surface(&plane->pending_fb, &plane->surf)) {
|
|
|
|
return false;
|
|
|
|
}
|
2018-03-11 11:40:03 +01:00
|
|
|
|
2018-05-01 22:38:04 +02:00
|
|
|
plane->cursor_enabled = true;
|
2018-03-11 11:40:03 +01:00
|
|
|
}
|
2017-08-07 11:07:42 +02:00
|
|
|
|
2018-02-02 21:01:59 +01:00
|
|
|
if (!drm->session->active) {
|
2018-03-11 11:40:03 +01:00
|
|
|
return true; // will be committed when session is resumed
|
2018-02-02 21:01:59 +01:00
|
|
|
}
|
|
|
|
|
2020-02-08 07:02:31 +01:00
|
|
|
struct gbm_bo *bo = NULL;
|
|
|
|
|
|
|
|
if (plane->cursor_enabled) {
|
|
|
|
bo = drm_fb_acquire(&plane->pending_fb, drm, &plane->mgpu_surf);
|
|
|
|
|
|
|
|
wlr_log(WLR_DEBUG, "SET_CURSOR %p %p", plane->pending_fb.bo, bo);
|
2019-02-05 23:39:30 +01:00
|
|
|
|
2020-02-08 07:02:31 +01:00
|
|
|
/* Workaround for nouveau buffers created with GBM_BO_USER_LINEAR are
|
|
|
|
* placed in NOUVEAU_GEM_DOMAIN_GART. When the bo is attached to the
|
|
|
|
* cursor plane it is moved to NOUVEAU_GEM_DOMAIN_VRAM. However, this
|
|
|
|
* does not wait for the render operations to complete, leaving an
|
|
|
|
* empty surface. See
|
|
|
|
* https://gitlab.freedesktop.org/xorg/driver/xf86-video-nouveau/issues/480
|
|
|
|
* The render operations can be waited for using:
|
|
|
|
*/
|
2019-02-15 15:59:09 +01:00
|
|
|
glFinish();
|
|
|
|
}
|
2020-02-08 07:02:31 +01:00
|
|
|
|
|
|
|
if (!drm->iface->crtc_set_cursor(drm, crtc, bo)) {
|
|
|
|
return false;
|
2018-01-20 16:43:14 +01:00
|
|
|
}
|
2020-02-08 07:02:31 +01:00
|
|
|
|
|
|
|
wlr_output_update_needs_frame(output);
|
|
|
|
return true;
|
2017-06-16 21:38:34 +02:00
|
|
|
}
|
|
|
|
|
2018-04-21 12:42:18 +02:00
|
|
|
static bool drm_connector_move_cursor(struct wlr_output *output,
|
2017-06-16 21:38:34 +02:00
|
|
|
int x, int y) {
|
2018-09-17 22:25:20 +02:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
2018-01-21 22:16:55 +01:00
|
|
|
if (!conn->crtc) {
|
2018-01-21 21:47:02 +01:00
|
|
|
return false;
|
|
|
|
}
|
2017-10-29 18:45:53 +01:00
|
|
|
struct wlr_drm_plane *plane = conn->crtc->cursor;
|
|
|
|
|
2018-01-26 22:11:09 +01:00
|
|
|
struct wlr_box box = { .x = x, .y = y };
|
|
|
|
|
|
|
|
int width, height;
|
2018-01-30 10:23:35 +01:00
|
|
|
wlr_output_transformed_resolution(output, &width, &height);
|
2017-08-20 22:02:39 +02:00
|
|
|
|
2017-11-01 14:25:41 +01:00
|
|
|
enum wl_output_transform transform =
|
|
|
|
wlr_output_transform_invert(output->transform);
|
2018-12-21 19:56:10 +01:00
|
|
|
wlr_box_transform(&box, &box, transform, width, height);
|
2017-08-20 22:02:39 +02:00
|
|
|
|
2017-12-05 22:23:01 +01:00
|
|
|
if (plane != NULL) {
|
2018-01-30 10:23:35 +01:00
|
|
|
box.x -= plane->cursor_hotspot_x;
|
|
|
|
box.y -= plane->cursor_hotspot_y;
|
2017-12-05 22:23:01 +01:00
|
|
|
}
|
2017-11-01 14:36:58 +01:00
|
|
|
|
2018-02-02 21:01:59 +01:00
|
|
|
conn->cursor_x = box.x;
|
|
|
|
conn->cursor_y = box.y;
|
|
|
|
|
2020-05-07 16:17:18 +02:00
|
|
|
wlr_output_update_needs_frame(output);
|
|
|
|
return true;
|
2017-06-16 21:38:34 +02:00
|
|
|
}
|
|
|
|
|
2018-04-21 12:42:18 +02:00
|
|
|
static void drm_connector_destroy(struct wlr_output *output) {
|
2018-09-17 22:25:20 +02:00
|
|
|
struct wlr_drm_connector *conn = get_drm_connector_from_output(output);
|
2018-04-21 12:42:18 +02:00
|
|
|
drm_connector_cleanup(conn);
|
2018-09-28 10:00:40 +02:00
|
|
|
drmModeFreeCrtc(conn->old_crtc);
|
2017-09-30 12:31:08 +02:00
|
|
|
wl_event_source_remove(conn->retry_pageflip);
|
2017-11-01 19:34:17 +01:00
|
|
|
wl_list_remove(&conn->link);
|
2017-09-30 12:31:08 +02:00
|
|
|
free(conn);
|
2017-05-07 18:26:48 +02:00
|
|
|
}
|
|
|
|
|
2018-04-21 12:42:18 +02:00
|
|
|
static const struct wlr_output_impl output_impl = {
|
|
|
|
.set_cursor = drm_connector_set_cursor,
|
|
|
|
.move_cursor = drm_connector_move_cursor,
|
|
|
|
.destroy = drm_connector_destroy,
|
2019-04-23 18:26:21 +02:00
|
|
|
.attach_render = drm_connector_attach_render,
|
2020-04-02 12:41:19 +02:00
|
|
|
.test = drm_connector_test,
|
2019-04-23 18:26:21 +02:00
|
|
|
.commit = drm_connector_commit,
|
2020-04-06 11:53:20 +02:00
|
|
|
.rollback = drm_connector_rollback,
|
2018-10-03 10:53:35 +02:00
|
|
|
.set_gamma = set_drm_connector_gamma,
|
2018-04-21 12:42:18 +02:00
|
|
|
.get_gamma_size = drm_connector_get_gamma_size,
|
2018-05-21 19:50:51 +02:00
|
|
|
.export_dmabuf = drm_connector_export_dmabuf,
|
2017-05-07 18:26:48 +02:00
|
|
|
};
|
|
|
|
|
2017-12-19 19:59:08 +01:00
|
|
|
bool wlr_output_is_drm(struct wlr_output *output) {
|
|
|
|
return output->impl == &output_impl;
|
|
|
|
}
|
|
|
|
|
2017-09-23 08:27:14 +02:00
|
|
|
static int retry_pageflip(void *data) {
|
2017-09-30 12:31:08 +02:00
|
|
|
struct wlr_drm_connector *conn = data;
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log(WLR_INFO, "%s: Retrying pageflip", conn->output.name);
|
2018-04-21 12:42:18 +02:00
|
|
|
drm_connector_start_renderer(conn);
|
2017-09-23 08:44:39 +02:00
|
|
|
return 0;
|
2017-09-23 08:27:14 +02:00
|
|
|
}
|
|
|
|
|
2017-07-20 13:26:53 +02:00
|
|
|
static const int32_t subpixel_map[] = {
|
|
|
|
[DRM_MODE_SUBPIXEL_UNKNOWN] = WL_OUTPUT_SUBPIXEL_UNKNOWN,
|
|
|
|
[DRM_MODE_SUBPIXEL_HORIZONTAL_RGB] = WL_OUTPUT_SUBPIXEL_HORIZONTAL_RGB,
|
|
|
|
[DRM_MODE_SUBPIXEL_HORIZONTAL_BGR] = WL_OUTPUT_SUBPIXEL_HORIZONTAL_BGR,
|
|
|
|
[DRM_MODE_SUBPIXEL_VERTICAL_RGB] = WL_OUTPUT_SUBPIXEL_VERTICAL_RGB,
|
|
|
|
[DRM_MODE_SUBPIXEL_VERTICAL_BGR] = WL_OUTPUT_SUBPIXEL_VERTICAL_BGR,
|
|
|
|
[DRM_MODE_SUBPIXEL_NONE] = WL_OUTPUT_SUBPIXEL_NONE,
|
|
|
|
};
|
2017-05-13 10:37:15 +02:00
|
|
|
|
2018-09-04 15:09:07 +02:00
|
|
|
static void dealloc_crtc(struct wlr_drm_connector *conn) {
|
2018-09-17 22:25:20 +02:00
|
|
|
struct wlr_drm_backend *drm =
|
|
|
|
get_drm_backend_from_backend(conn->output.backend);
|
2018-09-04 15:09:07 +02:00
|
|
|
if (conn->crtc == NULL) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-09-04 19:44:44 +02:00
|
|
|
wlr_log(WLR_DEBUG, "De-allocating CRTC %zu for output '%s'",
|
|
|
|
conn->crtc - drm->crtcs, conn->output.name);
|
|
|
|
|
2018-10-03 10:53:35 +02:00
|
|
|
set_drm_connector_gamma(&conn->output, 0, NULL, NULL, NULL);
|
2020-02-08 07:02:31 +01:00
|
|
|
drm_plane_finish_surface(conn->crtc->primary);
|
|
|
|
drm_plane_finish_surface(conn->crtc->cursor);
|
2018-09-04 15:09:07 +02:00
|
|
|
|
|
|
|
drm->iface->conn_enable(drm, conn, false);
|
|
|
|
|
|
|
|
conn->crtc = NULL;
|
|
|
|
}
|
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
static void realloc_crtcs(struct wlr_drm_backend *drm) {
|
|
|
|
assert(drm->num_crtcs > 0);
|
2018-09-04 15:09:07 +02:00
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
size_t num_outputs = wl_list_length(&drm->outputs);
|
|
|
|
if (num_outputs == 0) {
|
|
|
|
return;
|
2018-09-10 23:35:22 +02:00
|
|
|
}
|
|
|
|
|
2018-09-04 15:09:07 +02:00
|
|
|
wlr_log(WLR_DEBUG, "Reallocating CRTCs");
|
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
struct wlr_drm_connector *connectors[num_outputs];
|
|
|
|
uint32_t connector_constraints[num_outputs];
|
|
|
|
uint32_t previous_match[drm->num_crtcs];
|
|
|
|
uint32_t new_match[drm->num_crtcs];
|
|
|
|
|
2018-09-04 15:09:07 +02:00
|
|
|
for (size_t i = 0; i < drm->num_crtcs; ++i) {
|
2019-06-21 08:06:21 +02:00
|
|
|
previous_match[i] = UNMATCHED;
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
wlr_log(WLR_DEBUG, "State before reallocation:");
|
2019-06-21 08:06:21 +02:00
|
|
|
size_t i = 0;
|
2018-09-04 15:09:07 +02:00
|
|
|
struct wlr_drm_connector *conn;
|
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
2018-09-10 23:35:22 +02:00
|
|
|
connectors[i] = conn;
|
2018-09-04 15:09:07 +02:00
|
|
|
|
2018-09-10 23:35:22 +02:00
|
|
|
wlr_log(WLR_DEBUG, " '%s' crtc=%d state=%d desired_enabled=%d",
|
|
|
|
conn->output.name,
|
|
|
|
conn->crtc ? (int)(conn->crtc - drm->crtcs) : -1,
|
|
|
|
conn->state, conn->desired_enabled);
|
2018-09-04 15:09:07 +02:00
|
|
|
|
|
|
|
if (conn->crtc) {
|
2019-06-21 08:06:21 +02:00
|
|
|
previous_match[conn->crtc - drm->crtcs] = i;
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
|
|
|
|
2018-09-10 23:35:22 +02:00
|
|
|
// Only search CRTCs for user-enabled outputs (that are already
|
|
|
|
// connected or in need of a modeset)
|
|
|
|
if ((conn->state == WLR_DRM_CONN_CONNECTED ||
|
|
|
|
conn->state == WLR_DRM_CONN_NEEDS_MODESET) &&
|
|
|
|
conn->desired_enabled) {
|
2019-06-21 08:06:21 +02:00
|
|
|
connector_constraints[i] = conn->possible_crtc;
|
|
|
|
} else {
|
|
|
|
// Will always fail to match anything
|
|
|
|
connector_constraints[i] = 0;
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
2019-06-21 08:06:21 +02:00
|
|
|
|
|
|
|
++i;
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
match_obj(num_outputs, connector_constraints,
|
|
|
|
drm->num_crtcs, previous_match, new_match);
|
2018-09-04 15:09:07 +02:00
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
// Converts our crtc=>connector result into a connector=>crtc one.
|
|
|
|
ssize_t connector_match[num_outputs];
|
|
|
|
for (size_t i = 0 ; i < num_outputs; ++i) {
|
|
|
|
connector_match[i] = -1;
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
|
|
|
for (size_t i = 0; i < drm->num_crtcs; ++i) {
|
2019-06-21 08:06:21 +02:00
|
|
|
if (new_match[i] != UNMATCHED) {
|
|
|
|
connector_match[new_match[i]] = i;
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
/*
|
|
|
|
* In the case that we add a new connector (hotplug) and we fail to
|
|
|
|
* match everything, we prefer to fail the new connector and keep all
|
|
|
|
* of the old mappings instead.
|
|
|
|
*/
|
|
|
|
for (size_t i = 0; i < num_outputs; ++i) {
|
|
|
|
struct wlr_drm_connector *conn = connectors[i];
|
|
|
|
if (conn->state == WLR_DRM_CONN_CONNECTED &&
|
|
|
|
conn->desired_enabled &&
|
|
|
|
connector_match[i] == -1) {
|
|
|
|
wlr_log(WLR_DEBUG, "Could not match a CRTC for previously connected output; "
|
|
|
|
"keeping old configuration");
|
|
|
|
return;
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
wlr_log(WLR_DEBUG, "State after reallocation:");
|
2019-06-21 08:06:21 +02:00
|
|
|
|
|
|
|
// Apply new configuration
|
|
|
|
for (size_t i = 0; i < num_outputs; ++i) {
|
|
|
|
struct wlr_drm_connector *conn = connectors[i];
|
|
|
|
bool prev_enabled = conn->crtc;
|
|
|
|
|
|
|
|
wlr_log(WLR_DEBUG, " '%s' crtc=%zd state=%d desired_enabled=%d",
|
2018-09-10 23:35:22 +02:00
|
|
|
conn->output.name,
|
2019-06-21 08:06:21 +02:00
|
|
|
connector_match[i],
|
2018-09-10 23:35:22 +02:00
|
|
|
conn->state, conn->desired_enabled);
|
2018-09-04 15:09:07 +02:00
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
// We don't need to change anything.
|
|
|
|
if (prev_enabled && connector_match[i] == conn->crtc - drm->crtcs) {
|
|
|
|
continue;
|
|
|
|
}
|
2018-09-04 15:09:07 +02:00
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
dealloc_crtc(conn);
|
2018-09-04 15:09:07 +02:00
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
if (connector_match[i] == -1) {
|
|
|
|
if (prev_enabled) {
|
|
|
|
wlr_log(WLR_DEBUG, "Output has %s lost its CRTC",
|
|
|
|
conn->output.name);
|
|
|
|
conn->state = WLR_DRM_CONN_NEEDS_MODESET;
|
|
|
|
wlr_output_update_enabled(&conn->output, false);
|
|
|
|
conn->desired_mode = conn->output.current_mode;
|
|
|
|
wlr_output_update_mode(&conn->output, NULL);
|
|
|
|
}
|
2019-01-19 10:14:01 +01:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
conn->crtc = &drm->crtcs[connector_match[i]];
|
|
|
|
|
|
|
|
// Only realloc buffers if we have actually been modeset
|
|
|
|
if (conn->state != WLR_DRM_CONN_CONNECTED) {
|
2018-09-04 15:09:07 +02:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2019-10-22 18:41:47 +02:00
|
|
|
struct wlr_drm_mode *mode =
|
|
|
|
(struct wlr_drm_mode *)conn->output.current_mode;
|
|
|
|
if (!drm_connector_init_renderer(conn, mode)) {
|
2020-01-17 10:50:29 +01:00
|
|
|
wlr_log(WLR_ERROR, "Failed to initialize renderer on output %s",
|
|
|
|
conn->output.name);
|
|
|
|
wlr_output_update_enabled(&conn->output, false);
|
|
|
|
continue;
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
|
|
|
|
2018-09-04 23:10:37 +02:00
|
|
|
wlr_output_damage_whole(&conn->output);
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-12-09 10:48:00 +01:00
|
|
|
static uint32_t get_possible_crtcs(int fd, drmModeRes *res,
|
|
|
|
drmModeConnector *conn, bool is_mst) {
|
|
|
|
uint32_t ret = 0;
|
2018-09-04 15:09:07 +02:00
|
|
|
|
2018-12-09 10:55:53 +01:00
|
|
|
for (int i = 0; i < conn->count_encoders; ++i) {
|
|
|
|
drmModeEncoder *enc = drmModeGetEncoder(fd, conn->encoders[i]);
|
2018-12-09 10:48:00 +01:00
|
|
|
if (!enc) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret |= enc->possible_crtcs;
|
|
|
|
|
|
|
|
drmModeFreeEncoder(enc);
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
|
|
|
|
2018-12-09 10:48:00 +01:00
|
|
|
// Sometimes DP MST connectors report no encoders, so we'll loop though
|
|
|
|
// all of the encoders of the MST type instead.
|
|
|
|
// TODO: See if there is a better solution.
|
|
|
|
|
|
|
|
if (!is_mst || ret) {
|
|
|
|
return ret;
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
|
|
|
|
2018-12-09 10:48:00 +01:00
|
|
|
for (int i = 0; i < res->count_encoders; ++i) {
|
2018-12-09 10:55:53 +01:00
|
|
|
drmModeEncoder *enc = drmModeGetEncoder(fd, res->encoders[i]);
|
2018-12-09 10:48:00 +01:00
|
|
|
if (!enc) {
|
|
|
|
continue;
|
|
|
|
}
|
2018-09-04 15:09:07 +02:00
|
|
|
|
2018-12-09 10:48:00 +01:00
|
|
|
if (enc->encoder_type == DRM_MODE_ENCODER_DPMST) {
|
|
|
|
ret |= enc->possible_crtcs;
|
|
|
|
}
|
|
|
|
|
|
|
|
drmModeFreeEncoder(enc);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
2018-09-04 15:09:07 +02:00
|
|
|
}
|
|
|
|
|
2018-04-26 00:24:58 +02:00
|
|
|
void scan_drm_connectors(struct wlr_drm_backend *drm) {
|
2019-06-24 03:52:23 +02:00
|
|
|
/*
|
|
|
|
* This GPU is not really a modesetting device.
|
|
|
|
* It's just being used as a renderer.
|
|
|
|
*/
|
|
|
|
if (drm->num_crtcs == 0) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log(WLR_INFO, "Scanning DRM connectors");
|
2017-05-04 11:58:11 +02:00
|
|
|
|
2017-09-30 11:22:26 +02:00
|
|
|
drmModeRes *res = drmModeGetResources(drm->fd);
|
2017-05-03 12:40:19 +02:00
|
|
|
if (!res) {
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log_errno(WLR_ERROR, "Failed to get DRM resources");
|
2017-05-03 12:40:19 +02:00
|
|
|
return;
|
2017-05-03 07:49:03 +02:00
|
|
|
}
|
2017-05-01 05:20:48 +02:00
|
|
|
|
2018-09-02 09:00:21 +02:00
|
|
|
size_t seen_len = wl_list_length(&drm->outputs);
|
2017-10-22 12:45:23 +02:00
|
|
|
// +1 so length can never be 0, which is undefined behaviour.
|
|
|
|
// Last element isn't used.
|
2018-09-02 09:00:21 +02:00
|
|
|
bool seen[seen_len + 1];
|
2018-09-02 01:03:20 +02:00
|
|
|
memset(seen, false, sizeof(seen));
|
|
|
|
size_t new_outputs_len = 0;
|
2018-09-02 09:00:21 +02:00
|
|
|
struct wlr_drm_connector *new_outputs[res->count_connectors + 1];
|
2017-09-09 12:41:23 +02:00
|
|
|
|
2017-05-03 12:40:19 +02:00
|
|
|
for (int i = 0; i < res->count_connectors; ++i) {
|
2017-09-30 12:31:08 +02:00
|
|
|
drmModeConnector *drm_conn = drmModeGetConnector(drm->fd,
|
2017-07-20 13:26:53 +02:00
|
|
|
res->connectors[i]);
|
2017-09-30 12:31:08 +02:00
|
|
|
if (!drm_conn) {
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log_errno(WLR_ERROR, "Failed to get DRM connector");
|
2017-05-03 12:40:19 +02:00
|
|
|
continue;
|
2017-05-01 05:20:48 +02:00
|
|
|
}
|
2017-10-22 23:38:30 +02:00
|
|
|
drmModeEncoder *curr_enc = drmModeGetEncoder(drm->fd,
|
|
|
|
drm_conn->encoder_id);
|
|
|
|
|
2018-12-09 10:05:03 +01:00
|
|
|
ssize_t index = -1;
|
2017-10-19 15:48:00 +02:00
|
|
|
struct wlr_drm_connector *c, *wlr_conn = NULL;
|
|
|
|
wl_list_for_each(c, &drm->outputs, link) {
|
|
|
|
index++;
|
|
|
|
if (c->id == drm_conn->connector_id) {
|
|
|
|
wlr_conn = c;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2017-10-22 23:38:30 +02:00
|
|
|
|
2017-10-19 15:48:00 +02:00
|
|
|
if (!wlr_conn) {
|
2017-09-30 12:31:08 +02:00
|
|
|
wlr_conn = calloc(1, sizeof(*wlr_conn));
|
|
|
|
if (!wlr_conn) {
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log_errno(WLR_ERROR, "Allocation failed");
|
2017-10-22 23:38:30 +02:00
|
|
|
drmModeFreeEncoder(curr_enc);
|
2017-09-30 12:31:08 +02:00
|
|
|
drmModeFreeConnector(drm_conn);
|
2017-07-20 13:26:53 +02:00
|
|
|
continue;
|
2017-05-07 18:26:48 +02:00
|
|
|
}
|
2018-01-04 12:46:15 +01:00
|
|
|
wlr_output_init(&wlr_conn->output, &drm->backend, &output_impl,
|
|
|
|
drm->display);
|
2017-05-03 12:40:19 +02:00
|
|
|
|
2017-09-30 11:22:26 +02:00
|
|
|
struct wl_event_loop *ev = wl_display_get_event_loop(drm->display);
|
2017-09-30 12:31:08 +02:00
|
|
|
wlr_conn->retry_pageflip = wl_event_loop_add_timer(ev, retry_pageflip,
|
|
|
|
wlr_conn);
|
2017-09-23 08:27:14 +02:00
|
|
|
|
2017-09-30 12:31:08 +02:00
|
|
|
wlr_conn->state = WLR_DRM_CONN_DISCONNECTED;
|
|
|
|
wlr_conn->id = drm_conn->connector_id;
|
2017-05-03 12:40:19 +02:00
|
|
|
|
2018-09-04 15:09:07 +02:00
|
|
|
snprintf(wlr_conn->output.name, sizeof(wlr_conn->output.name),
|
|
|
|
"%s-%"PRIu32, conn_get_name(drm_conn->connector_type),
|
|
|
|
drm_conn->connector_type_id);
|
|
|
|
|
2017-05-04 11:58:11 +02:00
|
|
|
if (curr_enc) {
|
2017-09-30 12:31:08 +02:00
|
|
|
wlr_conn->old_crtc = drmModeGetCrtc(drm->fd, curr_enc->crtc_id);
|
2017-05-04 11:58:11 +02:00
|
|
|
}
|
|
|
|
|
2018-12-09 10:05:03 +01:00
|
|
|
wl_list_insert(drm->outputs.prev, &wlr_conn->link);
|
2018-09-04 15:09:07 +02:00
|
|
|
wlr_log(WLR_INFO, "Found connector '%s'", wlr_conn->output.name);
|
2017-05-03 12:40:19 +02:00
|
|
|
} else {
|
2017-09-09 12:41:23 +02:00
|
|
|
seen[index] = true;
|
2017-05-01 05:20:48 +02:00
|
|
|
}
|
|
|
|
|
2017-10-22 23:38:30 +02:00
|
|
|
if (curr_enc) {
|
|
|
|
for (size_t i = 0; i < drm->num_crtcs; ++i) {
|
|
|
|
if (drm->crtcs[i].id == curr_enc->crtc_id) {
|
|
|
|
wlr_conn->crtc = &drm->crtcs[i];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
wlr_conn->crtc = NULL;
|
|
|
|
}
|
|
|
|
|
2018-10-04 14:11:37 +02:00
|
|
|
// This can only happen *after* hotplug, since we haven't read the
|
|
|
|
// connector properties yet
|
|
|
|
if (wlr_conn->props.link_status != 0) {
|
|
|
|
uint64_t link_status;
|
|
|
|
if (!get_drm_prop(drm->fd, wlr_conn->id,
|
|
|
|
wlr_conn->props.link_status, &link_status)) {
|
|
|
|
wlr_log(WLR_ERROR, "Failed to get link status for '%s'",
|
|
|
|
wlr_conn->output.name);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (link_status == DRM_MODE_LINK_STATUS_BAD) {
|
|
|
|
// We need to reload our list of modes and force a modeset
|
|
|
|
wlr_log(WLR_INFO, "Bad link for '%s'", wlr_conn->output.name);
|
|
|
|
drm_connector_cleanup(wlr_conn);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-09-30 12:31:08 +02:00
|
|
|
if (wlr_conn->state == WLR_DRM_CONN_DISCONNECTED &&
|
|
|
|
drm_conn->connection == DRM_MODE_CONNECTED) {
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log(WLR_INFO, "'%s' connected", wlr_conn->output.name);
|
|
|
|
wlr_log(WLR_DEBUG, "Current CRTC: %d",
|
2018-05-27 12:32:00 +02:00
|
|
|
wlr_conn->crtc ? (int)wlr_conn->crtc->id : -1);
|
2018-02-06 22:45:37 +01:00
|
|
|
|
|
|
|
wlr_conn->output.phys_width = drm_conn->mmWidth;
|
|
|
|
wlr_conn->output.phys_height = drm_conn->mmHeight;
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log(WLR_INFO, "Physical size: %"PRId32"x%"PRId32,
|
2018-02-06 22:45:37 +01:00
|
|
|
wlr_conn->output.phys_width, wlr_conn->output.phys_height);
|
|
|
|
wlr_conn->output.subpixel = subpixel_map[drm_conn->subpixel];
|
|
|
|
|
2018-04-26 00:24:58 +02:00
|
|
|
get_drm_connector_props(drm->fd, wlr_conn->id, &wlr_conn->props);
|
2018-02-06 22:45:37 +01:00
|
|
|
|
|
|
|
size_t edid_len = 0;
|
2018-04-26 00:24:58 +02:00
|
|
|
uint8_t *edid = get_drm_prop_blob(drm->fd,
|
2018-02-06 22:45:37 +01:00
|
|
|
wlr_conn->id, wlr_conn->props.edid, &edid_len);
|
|
|
|
parse_edid(&wlr_conn->output, edid_len, edid);
|
|
|
|
free(edid);
|
|
|
|
|
2019-12-26 16:09:05 +01:00
|
|
|
struct wlr_output *output = &wlr_conn->output;
|
|
|
|
char description[128];
|
|
|
|
snprintf(description, sizeof(description), "%s %s %s (%s)",
|
|
|
|
output->make, output->model, output->serial, output->name);
|
|
|
|
wlr_output_set_description(output, description);
|
|
|
|
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log(WLR_INFO, "Detected modes:");
|
2017-05-03 12:40:19 +02:00
|
|
|
|
2017-09-30 12:31:08 +02:00
|
|
|
for (int i = 0; i < drm_conn->count_modes; ++i) {
|
|
|
|
struct wlr_drm_mode *mode = calloc(1, sizeof(*mode));
|
2017-08-16 09:23:21 +02:00
|
|
|
if (!mode) {
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log_errno(WLR_ERROR, "Allocation failed");
|
2017-08-16 09:23:21 +02:00
|
|
|
continue;
|
|
|
|
}
|
2018-11-21 20:23:48 +01:00
|
|
|
|
2018-11-22 18:52:52 +01:00
|
|
|
if (drm_conn->modes[i].flags & DRM_MODE_FLAG_INTERLACE) {
|
2018-11-21 20:23:48 +01:00
|
|
|
free(mode);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2017-09-30 12:31:08 +02:00
|
|
|
mode->drm_mode = drm_conn->modes[i];
|
|
|
|
mode->wlr_mode.width = mode->drm_mode.hdisplay;
|
|
|
|
mode->wlr_mode.height = mode->drm_mode.vdisplay;
|
|
|
|
mode->wlr_mode.refresh = calculate_refresh_rate(&mode->drm_mode);
|
2019-03-21 21:12:43 +01:00
|
|
|
if (mode->drm_mode.type & DRM_MODE_TYPE_PREFERRED) {
|
|
|
|
mode->wlr_mode.preferred = true;
|
|
|
|
}
|
2017-05-03 12:40:19 +02:00
|
|
|
|
2019-12-20 10:56:59 +01:00
|
|
|
wlr_log(WLR_INFO, " %"PRId32"x%"PRId32"@%"PRId32" %s",
|
2017-08-14 14:03:51 +02:00
|
|
|
mode->wlr_mode.width, mode->wlr_mode.height,
|
2019-12-20 10:56:59 +01:00
|
|
|
mode->wlr_mode.refresh,
|
|
|
|
mode->wlr_mode.preferred ? "(preferred)" : "");
|
2017-05-01 05:20:48 +02:00
|
|
|
|
2017-10-15 12:32:37 +02:00
|
|
|
wl_list_insert(&wlr_conn->output.modes, &mode->wlr_mode.link);
|
2017-05-03 07:49:03 +02:00
|
|
|
}
|
2017-05-01 05:20:48 +02:00
|
|
|
|
2019-09-03 16:06:49 +02:00
|
|
|
size_t path_len;
|
|
|
|
bool is_mst = false;
|
|
|
|
char *path = get_drm_prop_blob(drm->fd, wlr_conn->id,
|
|
|
|
wlr_conn->props.path, &path_len);
|
|
|
|
if (path_len > 4 && path && strncmp(path, "mst:", 4) == 0) {
|
|
|
|
is_mst = true;
|
|
|
|
}
|
|
|
|
free(path);
|
|
|
|
|
2018-12-09 10:48:00 +01:00
|
|
|
wlr_conn->possible_crtc = get_possible_crtcs(drm->fd, res, drm_conn,
|
2019-09-03 16:06:49 +02:00
|
|
|
is_mst);
|
2018-09-04 15:09:07 +02:00
|
|
|
if (wlr_conn->possible_crtc == 0) {
|
|
|
|
wlr_log(WLR_ERROR, "No CRTC possible for connector '%s'",
|
|
|
|
wlr_conn->output.name);
|
|
|
|
}
|
|
|
|
|
2019-12-29 10:55:16 +01:00
|
|
|
// TODO: this results in connectors being enabled without a mode
|
|
|
|
// set
|
2018-09-02 01:03:20 +02:00
|
|
|
wlr_output_update_enabled(&wlr_conn->output, wlr_conn->crtc != NULL);
|
2018-09-10 23:35:22 +02:00
|
|
|
wlr_conn->desired_enabled = true;
|
2017-10-22 22:21:23 +02:00
|
|
|
|
2017-09-30 12:31:08 +02:00
|
|
|
wlr_conn->state = WLR_DRM_CONN_NEEDS_MODESET;
|
2018-09-02 01:03:20 +02:00
|
|
|
new_outputs[new_outputs_len++] = wlr_conn;
|
2018-12-09 10:05:03 +01:00
|
|
|
} else if ((wlr_conn->state == WLR_DRM_CONN_CONNECTED ||
|
|
|
|
wlr_conn->state == WLR_DRM_CONN_NEEDS_MODESET) &&
|
2017-09-30 12:31:08 +02:00
|
|
|
drm_conn->connection != DRM_MODE_CONNECTED) {
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log(WLR_INFO, "'%s' disconnected", wlr_conn->output.name);
|
2017-10-22 22:21:23 +02:00
|
|
|
|
2018-04-21 12:42:18 +02:00
|
|
|
drm_connector_cleanup(wlr_conn);
|
2017-05-01 05:20:48 +02:00
|
|
|
}
|
|
|
|
|
2017-10-22 23:38:30 +02:00
|
|
|
drmModeFreeEncoder(curr_enc);
|
2017-09-30 12:31:08 +02:00
|
|
|
drmModeFreeConnector(drm_conn);
|
2017-05-01 05:20:48 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
drmModeFreeResources(res);
|
2017-09-09 12:41:23 +02:00
|
|
|
|
2018-12-09 10:05:03 +01:00
|
|
|
// Iterate in reverse order because we'll remove items from the list and
|
|
|
|
// still want indices to remain correct.
|
2017-10-19 15:48:00 +02:00
|
|
|
struct wlr_drm_connector *conn, *tmp_conn;
|
2017-10-22 12:45:23 +02:00
|
|
|
size_t index = wl_list_length(&drm->outputs);
|
2018-12-09 10:05:03 +01:00
|
|
|
wl_list_for_each_reverse_safe(conn, tmp_conn, &drm->outputs, link) {
|
2017-10-22 12:45:23 +02:00
|
|
|
index--;
|
2018-09-02 09:00:21 +02:00
|
|
|
if (index >= seen_len || seen[index]) {
|
2017-09-09 12:41:23 +02:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log(WLR_INFO, "'%s' disappeared", conn->output.name);
|
2018-04-21 12:42:18 +02:00
|
|
|
drm_connector_cleanup(conn);
|
2017-09-09 12:41:23 +02:00
|
|
|
|
2019-08-02 19:11:23 +02:00
|
|
|
wlr_output_destroy(&conn->output);
|
2017-09-09 12:41:23 +02:00
|
|
|
}
|
2018-09-02 01:03:20 +02:00
|
|
|
|
2019-06-21 08:06:21 +02:00
|
|
|
realloc_crtcs(drm);
|
2018-09-04 15:09:07 +02:00
|
|
|
|
2018-09-02 01:03:20 +02:00
|
|
|
for (size_t i = 0; i < new_outputs_len; ++i) {
|
|
|
|
struct wlr_drm_connector *conn = new_outputs[i];
|
|
|
|
|
|
|
|
wlr_log(WLR_INFO, "Requesting modeset for '%s'",
|
|
|
|
conn->output.name);
|
|
|
|
wlr_signal_emit_safe(&drm->backend.events.new_output,
|
|
|
|
&conn->output);
|
|
|
|
}
|
2018-09-04 15:09:07 +02:00
|
|
|
|
2018-09-10 23:35:22 +02:00
|
|
|
attempt_enable_needs_modeset(drm);
|
2017-05-01 05:20:48 +02:00
|
|
|
}
|
|
|
|
|
2018-10-02 12:11:09 +02:00
|
|
|
static int mhz_to_nsec(int mhz) {
|
|
|
|
return 1000000000000LL / mhz;
|
|
|
|
}
|
|
|
|
|
2017-05-07 16:00:23 +02:00
|
|
|
static void page_flip_handler(int fd, unsigned seq,
|
2019-06-26 17:14:31 +02:00
|
|
|
unsigned tv_sec, unsigned tv_usec, unsigned crtc_id, void *data) {
|
|
|
|
struct wlr_drm_backend *drm = data;
|
2020-02-08 07:02:31 +01:00
|
|
|
|
2019-06-26 17:14:31 +02:00
|
|
|
struct wlr_drm_connector *conn = NULL;
|
|
|
|
struct wlr_drm_connector *search;
|
|
|
|
wl_list_for_each(search, &drm->outputs, link) {
|
|
|
|
if (search->crtc && search->crtc->id == crtc_id) {
|
|
|
|
conn = search;
|
2020-02-08 07:02:31 +01:00
|
|
|
break;
|
2019-06-26 17:14:31 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!conn) {
|
2019-08-02 19:11:23 +02:00
|
|
|
wlr_log(WLR_DEBUG, "No connector for crtc_id %u", crtc_id);
|
2019-06-26 17:14:31 +02:00
|
|
|
return;
|
|
|
|
}
|
2017-05-03 12:40:19 +02:00
|
|
|
|
2017-09-30 12:31:08 +02:00
|
|
|
conn->pageflip_pending = false;
|
2018-09-28 10:00:40 +02:00
|
|
|
|
2018-09-10 23:35:22 +02:00
|
|
|
if (conn->state != WLR_DRM_CONN_CONNECTED || conn->crtc == NULL) {
|
2017-08-11 01:12:41 +02:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2020-02-08 07:02:31 +01:00
|
|
|
struct wlr_drm_plane *plane = conn->crtc->primary;
|
|
|
|
if (plane->queued_fb.type != WLR_DRM_FB_TYPE_NONE) {
|
|
|
|
drm_fb_move(&plane->current_fb, &plane->queued_fb);
|
|
|
|
}
|
|
|
|
if (conn->crtc->cursor &&
|
|
|
|
conn->crtc->cursor->queued_fb.type != WLR_DRM_FB_TYPE_NONE) {
|
|
|
|
drm_fb_move(&conn->crtc->cursor->current_fb,
|
|
|
|
&conn->crtc->cursor->queued_fb);
|
2019-10-22 19:29:18 +02:00
|
|
|
}
|
|
|
|
|
2019-05-04 11:07:37 +02:00
|
|
|
uint32_t present_flags = WLR_OUTPUT_PRESENT_VSYNC |
|
|
|
|
WLR_OUTPUT_PRESENT_HW_CLOCK | WLR_OUTPUT_PRESENT_HW_COMPLETION;
|
2020-02-08 07:02:31 +01:00
|
|
|
/* Don't report ZERO_COPY in multi-gpu situations, because we had to copy
|
|
|
|
* data between the GPUs, even if we were using the direct scanout
|
|
|
|
* interface.
|
|
|
|
*/
|
|
|
|
if (!drm->parent && plane->current_fb.type == WLR_DRM_FB_TYPE_WLR_BUFFER) {
|
2019-05-04 11:07:37 +02:00
|
|
|
present_flags |= WLR_OUTPUT_PRESENT_ZERO_COPY;
|
2017-06-09 07:15:55 +02:00
|
|
|
}
|
|
|
|
|
2018-09-29 22:38:13 +02:00
|
|
|
struct timespec present_time = {
|
|
|
|
.tv_sec = tv_sec,
|
|
|
|
.tv_nsec = tv_usec * 1000,
|
|
|
|
};
|
2018-10-02 12:11:09 +02:00
|
|
|
struct wlr_output_event_present present_event = {
|
2019-11-16 22:15:33 +01:00
|
|
|
/* The DRM backend guarantees that the presentation event will be for
|
|
|
|
* the last submitted frame. */
|
|
|
|
.commit_seq = conn->output.commit_seq,
|
2018-10-02 12:11:09 +02:00
|
|
|
.when = &present_time,
|
|
|
|
.seq = seq,
|
|
|
|
.refresh = mhz_to_nsec(conn->output.refresh),
|
2019-05-04 11:07:37 +02:00
|
|
|
.flags = present_flags,
|
2018-10-02 12:11:09 +02:00
|
|
|
};
|
|
|
|
wlr_output_send_present(&conn->output, &present_event);
|
2018-09-29 22:38:13 +02:00
|
|
|
|
2017-09-30 11:22:26 +02:00
|
|
|
if (drm->session->active) {
|
2018-01-26 22:39:23 +01:00
|
|
|
wlr_output_send_frame(&conn->output);
|
2017-05-03 07:49:03 +02:00
|
|
|
}
|
2017-05-03 12:40:19 +02:00
|
|
|
}
|
2017-05-01 05:20:48 +02:00
|
|
|
|
2018-04-26 00:24:58 +02:00
|
|
|
int handle_drm_event(int fd, uint32_t mask, void *data) {
|
2017-05-03 12:40:19 +02:00
|
|
|
drmEventContext event = {
|
2019-06-26 17:14:31 +02:00
|
|
|
.version = 3,
|
|
|
|
.page_flip_handler2 = page_flip_handler,
|
2017-05-03 12:40:19 +02:00
|
|
|
};
|
2017-05-01 07:49:18 +02:00
|
|
|
|
2017-05-03 12:40:19 +02:00
|
|
|
drmHandleEvent(fd, &event);
|
|
|
|
return 1;
|
|
|
|
}
|
2017-05-02 03:00:25 +02:00
|
|
|
|
2018-04-26 00:24:58 +02:00
|
|
|
void restore_drm_outputs(struct wlr_drm_backend *drm) {
|
2019-08-09 15:20:52 +02:00
|
|
|
uint64_t to_close = (UINT64_C(1) << wl_list_length(&drm->outputs)) - 1;
|
2017-09-23 06:32:25 +02:00
|
|
|
|
2017-10-19 15:48:00 +02:00
|
|
|
struct wlr_drm_connector *conn;
|
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
2017-09-30 12:31:08 +02:00
|
|
|
if (conn->state == WLR_DRM_CONN_CONNECTED) {
|
|
|
|
conn->state = WLR_DRM_CONN_CLEANUP;
|
2017-09-23 06:32:25 +02:00
|
|
|
}
|
2017-05-04 11:58:11 +02:00
|
|
|
}
|
|
|
|
|
2017-09-23 06:32:25 +02:00
|
|
|
time_t timeout = time(NULL) + 5;
|
|
|
|
|
|
|
|
while (to_close && time(NULL) < timeout) {
|
2018-04-26 00:24:58 +02:00
|
|
|
handle_drm_event(drm->fd, 0, NULL);
|
2017-10-19 15:48:00 +02:00
|
|
|
size_t i = 0;
|
|
|
|
struct wlr_drm_connector *conn;
|
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
2017-09-30 12:31:08 +02:00
|
|
|
if (conn->state != WLR_DRM_CONN_CLEANUP || !conn->pageflip_pending) {
|
2019-08-09 15:20:52 +02:00
|
|
|
to_close &= ~(UINT64_C(1) << i);
|
2017-09-23 06:32:25 +02:00
|
|
|
}
|
2017-10-19 15:48:00 +02:00
|
|
|
i++;
|
2017-09-23 06:32:25 +02:00
|
|
|
}
|
2017-05-03 07:49:03 +02:00
|
|
|
}
|
2017-05-02 03:00:25 +02:00
|
|
|
|
2017-09-23 06:32:25 +02:00
|
|
|
if (to_close) {
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log(WLR_ERROR, "Timed out stopping output renderers");
|
2017-09-23 06:32:25 +02:00
|
|
|
}
|
|
|
|
|
2017-10-19 15:48:00 +02:00
|
|
|
wl_list_for_each(conn, &drm->outputs, link) {
|
2017-09-30 12:31:08 +02:00
|
|
|
drmModeCrtc *crtc = conn->old_crtc;
|
2017-09-23 06:32:25 +02:00
|
|
|
if (!crtc) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
drmModeSetCrtc(drm->fd, crtc->crtc_id, crtc->buffer_id, crtc->x, crtc->y,
|
2017-09-30 12:31:08 +02:00
|
|
|
&conn->id, 1, &crtc->mode);
|
2019-02-24 05:00:49 +01:00
|
|
|
drmModeSetCursor(drm->fd, crtc->crtc_id, 0, 0, 0);
|
2017-09-23 06:32:25 +02:00
|
|
|
}
|
2017-05-01 05:20:48 +02:00
|
|
|
}
|
|
|
|
|
2018-04-21 12:42:18 +02:00
|
|
|
static void drm_connector_cleanup(struct wlr_drm_connector *conn) {
|
2017-09-30 12:31:08 +02:00
|
|
|
if (!conn) {
|
2017-05-03 12:40:19 +02:00
|
|
|
return;
|
|
|
|
}
|
2017-05-01 05:20:48 +02:00
|
|
|
|
2017-09-30 12:31:08 +02:00
|
|
|
switch (conn->state) {
|
|
|
|
case WLR_DRM_CONN_CONNECTED:
|
2019-06-21 08:06:21 +02:00
|
|
|
case WLR_DRM_CONN_CLEANUP:
|
2018-05-27 12:32:00 +02:00
|
|
|
conn->output.current_mode = NULL;
|
2018-09-04 15:09:07 +02:00
|
|
|
conn->desired_mode = NULL;
|
2018-05-27 12:32:00 +02:00
|
|
|
struct wlr_drm_mode *mode, *tmp;
|
2018-02-06 22:45:37 +01:00
|
|
|
wl_list_for_each_safe(mode, tmp, &conn->output.modes, wlr_mode.link) {
|
|
|
|
wl_list_remove(&mode->wlr_mode.link);
|
|
|
|
free(mode);
|
|
|
|
}
|
|
|
|
|
2018-09-04 15:09:07 +02:00
|
|
|
conn->output.enabled = false;
|
|
|
|
conn->output.width = conn->output.height = conn->output.refresh = 0;
|
|
|
|
|
2018-02-06 22:45:37 +01:00
|
|
|
memset(&conn->output.make, 0, sizeof(conn->output.make));
|
|
|
|
memset(&conn->output.model, 0, sizeof(conn->output.model));
|
|
|
|
memset(&conn->output.serial, 0, sizeof(conn->output.serial));
|
|
|
|
|
2018-10-09 10:25:38 +02:00
|
|
|
if (conn->output.idle_frame != NULL) {
|
|
|
|
wl_event_source_remove(conn->output.idle_frame);
|
|
|
|
conn->output.idle_frame = NULL;
|
|
|
|
}
|
2019-04-23 19:22:42 +02:00
|
|
|
conn->output.needs_frame = false;
|
2018-10-09 10:25:38 +02:00
|
|
|
conn->output.frame_pending = false;
|
|
|
|
|
2017-05-03 12:40:19 +02:00
|
|
|
/* Fallthrough */
|
2017-09-30 12:31:08 +02:00
|
|
|
case WLR_DRM_CONN_NEEDS_MODESET:
|
2018-07-09 23:49:54 +02:00
|
|
|
wlr_log(WLR_INFO, "Emitting destruction signal for '%s'",
|
2018-02-12 10:36:43 +01:00
|
|
|
conn->output.name);
|
2018-09-04 15:09:07 +02:00
|
|
|
dealloc_crtc(conn);
|
|
|
|
conn->possible_crtc = 0;
|
|
|
|
conn->desired_mode = NULL;
|
2020-05-01 15:15:40 +02:00
|
|
|
conn->pageflip_pending = false;
|
2018-02-12 10:36:43 +01:00
|
|
|
wlr_signal_emit_safe(&conn->output.events.destroy, &conn->output);
|
2017-05-03 12:40:19 +02:00
|
|
|
break;
|
2017-09-30 12:31:08 +02:00
|
|
|
case WLR_DRM_CONN_DISCONNECTED:
|
2017-05-03 12:40:19 +02:00
|
|
|
break;
|
|
|
|
}
|
2017-09-24 01:06:00 +02:00
|
|
|
|
2017-09-30 12:31:08 +02:00
|
|
|
conn->state = WLR_DRM_CONN_DISCONNECTED;
|
2017-05-13 10:37:15 +02:00
|
|
|
}
|